# US 7,609,021 B2 · Method and arrangement for monitoring signals

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- Number: US 7,609,021 B2
- Document ID: US7609021B2
- Status: Granted
- Kind: B2
- Application number: 11/922,163
- Filed: 2006-06-13
- Published: 2009-02-19
- Granted: 2009-10-27
- Earliest claimed: 2005-06-20
- Assignees: Siemens VDO Automotive Corporation
- Inventors: Wolfgang Bay; Michael Henninger; Sven Kretschmar
- Web page: https://patentgrep.com/patent/US7609021B2

## CPC

- H02P 29/02: Providing protection against overload without automatic interruption of supply (protection against faults of stepper motors H02P8/36)
- H02H 7/0844: {Fail safe control, e.g. by comparing control signal and controlled current, isolating motor on commutation error}
- H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

The invention relates to a method and to an arrangement for monitoring signals which are guided to a multi-phase motor by an end stage and the pulse width thereof is controlled by a controller. The total of the pulse widths of the signals of each phase is measured by, respectively, a counter, respectively for a predetermined program flow in the controller. The meter reading is read by a counter according to a predetermined period of time and an error signal is produced if the total amount of time exceeds a predetermined tolerance range.

## Claims

### Claim 1

A method of monitoring signals which are supplied from an output stage to a multiphase motor, the pulse width of the signals being controlled by a controller, the method comprising the steps of:
generating, by a timer, a gate pulse;
measuring, within a predetermined time period corresponding to the gate pulse, a sum of the pulse widths for each phase of the signals which are supplied from an output stage to a multiphase motor, the step of measuring being performed independently of a program sequence in the controller which controls the signals, said measuring comprising one of:
combining each of the signals with the gate pulse, sending the combined signals to respective counters, and reading the counters after the predetermined amount of time; or
sending each of the signals to respective counters, sending the gate pulse to the counters, enabling the counters for the duration of the gate pulse; and
generating a fault signal if the measured sum is outside a predetermined tolerance range.

### Claim 2 (depends on 1)

The method of claim 1, wherein the predefined tolerance range depends on the pulse width designated by the controller.

### Claim 3 (depends on 2)

The method of claim 2, wherein changes to the pulse width by the control circuit are accounted for in the predetermined tolerance range.

### Claim 4 (depends on 1)

The method of claim 1, wherein the predetermined amount of time is defined by the controller.

### Claim 5 (depends on 1)

The method of claim 1, wherein the gate pulse is asynchronous with respect to the pulses of the signals and has a length of an integer multiple of the period duration of the pulses.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gate pulse is synchronous with the pulses of the signals and has a length equal to a plurality of period durations of the pulses.

### Claim 7

An arrangement for monitoring signals which are supplied from an output stage to a multiphase motor, comprising:
a controller controlling the pulse width of pulses in signals supplied to a multiphase motor;
counters measuring a sum of pulse widths of the pulses in respective ones of the signals supplied to the multiphase motor for a predetermined amount of time;
a timer generating a gate pulse corresponding to the predetermined amount of time, the gate pulse being connected to one of a gate circuit for controlling the gate circuit to pass the signals to the counters for the duration of the gate pulse, or the counters for enabling the counters for the duration of the gate pulse,
means for reading the counters and generating a fault signal if the counter reading is outside of a predetermined tolerance range.

### Claim 8 (depends on 7)

The arrangement of claim 7, wherein the counters and timer form an integrated circuit with the controller.

### Claim 9 (depends on 7)

The arrangement of claim 7, wherein the counter and the timer each comprise a hardware counter.

### Claim 10 (depends on 7)

The arrangement of claim 7, wherein the counter and timer are part of a programmable device.

### Claim 11 (depends on 7)

The arrangement of claim 7, wherein the counter and timer are part of a mask-programmed circuit.

### Claim 12 (depends on 7)

The arrangement of claim 7, further comprising a comparator which compares the counter reading with a tolerance range determined by the controller, said comparator generating a fault signal if the counter reading is outside of the tolerance band.