# US 7,608,930 B2 · Semiconductor device and method of manufacturing semiconductor device

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- Number: US 7,608,930 B2
- Document ID: US7608930B2
- Status: Granted
- Kind: B2
- Application number: 12/078,772
- Filed: 2008-04-04
- Published: 2008-10-09
- Granted: 2009-10-27
- Earliest claimed: 2007-04-05
- Assignees: Rohm Co., Ltd.
- Inventors: Yasumasa Kasuya; Motoharu Haga
- Web page: https://patentgrep.com/patent/US7608930B2

## CPC

- H05K 3/3442: {having edge contacts, e.g. leadless chip capacitors, chip carriers}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 74/114: {by a substrate and the encapsulations}
- H05K 2201/10727: Leadless chip carrier [LCC], e.g. chip-modules for cards
- H05K 2201/10909: Materials of terminal, e.g. of leads or electrodes of components
- H10W 72/0198: {batch processes}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/5522: {comprising gold [Au]}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

This semiconductor device includes a semiconductor chip, and a lead arranged around the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to a package board, wherein a joint surface to the package board and an end surface orthogonal to the joint surface are formed on the end of the lead farther from the semiconductor chip, and a metal plating layer made of a pure metal is formed on the end surface.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor chip; and
a lead arranged around the semiconductor chip to extend in a direction intersecting with a side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to a package board, wherein
a joint surface to the package board and an end surface orthogonal to the joint surface are formed on the end of the lead farther from the semiconductor chip,
a first metal plating layer is formed on the joint surface, and
a second metal plating layer made of a pure metal different from a metal forming the first metal plating layer is formed on the end surface wherein the first and the second metal plating layers are in direct contact with the lead.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the second metal plating layer is made of a pure metal having a melting point of not more than 260° C.

### Claim 3

A method of manufacturing a semiconductor device using a lead frame integrally comprising a die pad, a lead arranged around the die pad to extend in a direction opposed to the die pad and a support portion connected with an end of the lead farther from the die pad, comprising:
a bonding step of die-bonding a semiconductor chip onto the die pad and electrically connecting the semiconductor chip and the lead with each other with a bonding wire;
a sealing step of sealing the semiconductor chip with sealing resin along with the lead frame so that a second surface of the lead opposite to a first surface connected with the bonding wire is exposed from the sealing resin after the bonding step;
a first plating step of forming a first metal plating layer on the exposed second surface of the lead by electrolytic plating after the sealing step:
a removing step of removing the support portion and the sealing resin on the support portion and exposing a third surface of the lead orthogonal to the second surface from the sealing resin; and
a second plating step of forming a second metal plating layer made of a pure metal different from a metal forming the first metal plating layer on the exposed third surface of the lead by electroless plating.

### Claim 4 (depends on 3)

The method of manufacturing a semiconductor device according to claim 3, wherein
the removing step is a step of removing the support portion and the sealing resin on the support portion by cutting with a dicing saw, and
the method further comprises an etching step for removing a flash formed on the lead in the removing step by etching in advance of the second plating step.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
the thickness of the second metal plating layer is not more than 3 μm.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
the second metal plating layer is made of tin (Sn) or indium (In).

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein
the semiconductor device further comprises a die pad supporting the semiconductor chip and having a lower surface bonded to the package board,
a third metal plating layer made of a metal same as the metal forming the first metal plating layer is formed on the lower surface of the die pad, and
the first and third metal plating layers are made of tin (Sn), a tin-silver alloy (Sn—Ag), a tin-bismuth alloy (Sn—Bi), a tin-copper alloy (Sn—Cu) or palladium (Pd), each.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein
the thickness of the first and third metal plating layers is not more than 15 μm.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein
the lead is made of copper (Cu) or 42 alloy.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein
the semiconductor device further comprises a die pad supporting the semiconductor chip,
the lead is in an elongated form in a direction opposite to the die pad, and has a body portion, the body portion having a lower surface that defines the joint surface, the lead further having a stop portion at an end closer to the die pad, the stop portion having an upper surface that is flush with an upper surface of the body portion, and a lower surface that is recessed relative to the lower surface of the body portion.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the first metal plating layer is formed primarily on the joint surface so as to not be on the end surface, and the second metal plating layer is formed primarily on the end surface to adjoin the first metal plating layer.

### Claim 12 (depends on 3)

The method of manufacturing a semiconductor device according to claim 3, wherein the first metal plating layer is formed primarily on the exposed second surface so as to not be on the third surface, and the second metal plating layer is formed primarily on the exposed third surface to adjoin the first metal plating layer.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, wherein the first metal plating layer is formed directly on the joint surface, and the second metal plating layer is formed directly on the end surface.

### Claim 14 (depends on 3)

The method of manufacturing a semiconductor device, according to claim 3, wherein the first metal plating layer is formed directly on the exposed second surface, and the second metal plating layer is formed directly on the exposed third surface.