# US 7,608,927 B2 · Localized biasing for silicon on insulator structures

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- Number: US 7,608,927 B2
- Document ID: US7608927B2
- Status: Granted
- Kind: B2
- Application number: 10/230,938
- Filed: 2002-08-29
- Published: 2004-03-04
- Granted: 2009-10-27
- Earliest claimed: 2002-08-29
- Assignees: Micron Technology, Inc.
- Inventors: Fernando Gonzalez; John K. Zahurak
- Web page: https://patentgrep.com/patent/US7608927B2

## CPC

- H10D 86/01: Manufacture or treatment
- H10B 12/036: {the capacitor extending under the transistor}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 89/211: {Design considerations for internal polarisation (integrated injection logic H10D84/65)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

## Claims

### Claim 1

A silicon-on-insulator semiconductor device, comprising:
a substrate configured to include a substrate potential;
an insulator in contact with the substrate;
a patterned conductor layer within the insulator and not extending vertically above the insulator and electrically insulated from the substrate, the patterned conductor layer includes a voltage biased, local portion;
a silicon layer formed on and in contact with the insulator and the patterned conductor layer, wherein the voltage biased, local portion is configured to adjust a bias potential of the silicon layer independent of the substrate potential;
at least one integrated circuit device formed in the silicon layer; and
wherein the voltage biased, local portion has a horizontal dimension greater than a horizontal dimension of the integrated circuit device.

### Claim 2 (depends on 1)

The device of claim 1, wherein the voltage biased, local portion of the patterned conductor layer is positioned to provide a localized bias voltage to a portion of the silicon layer adjacent the portion of the patterned conductor layer.

### Claim 3 (depends on 2)

The device of claim 2, wherein the bias voltage is ground.

### Claim 4 (depends on 2)

The device of claim 2, wherein the bias voltage includes a booted external voltage.

### Claim 5 (depends on 2)

The device of claim 2, wherein the substrate includes at least one second integrated circuit device, and the insulator is formed on the at least one second integrated circuit device.

### Claim 6 (depends on 5)

The device of claim 5, wherein the at least one second integrated circuit device includes an electrical energy storage device.

### Claim 7 (depends on 5)

The device of claim 5, wherein the insulator includes a buried oxide that is adapted to electrical isolate the patterned conductor layer from the at least one second integrated circuit.

### Claim 8 (depends on 1)

The device of claim 1, wherein the patterned conductor layer includes polysilicon.

### Claim 9 (depends on 1)

The device of claim 1, wherein the insulator includes a buried oxide.

### Claim 10 (depends on 1)

The device of claim 1, wherein the patterned conductor layer is adapted to provide a bias voltage to the at least one integrated circuit device.

### Claim 11 (depends on 1)

The silicon-on-insulator semiconductor device of claim 1, wherein the integrated circuit device is on the patterned conductor layer.

### Claim 12 (depends on 1)

The silicon-on-insulator semiconductor device of claim 1, wherein the conductor layer has a top surface substantially planar with the top surface of the insulator, and the silicon layer being on the top surfaces of both the conductor layer and the insulator layer.

### Claim 13 (depends on 1)

The silicon-on-insulator semiconductor device of claim 1, wherein the voltage biased, local portion is configured to electrically decouple the silicon layer from the substrate.

### Claim 14

A silicon-on-insulator semiconductor device, comprising:
a substrate configured to include a substrate potential;
an insulator in contact with the substrate;
a patterned conductor within the insulator and defining a plurality of voltage biasing portions electrically insulated from the substrate;
a silicon layer formed on and in contact with the insulator and the patterned conductor, wherein the plurality of voltage biasing portions are configured to provide a localized bias voltage to a different region of the silicon layer independent of the substrate potential; and
at least one integrated circuit device formed in the silicon layer; wherein the patterned conductor provides the localized bias voltage through one of the plurality of voltage biasing portions to the integrated circuit device, and wherein the one voltage biasing portion has a horizontal dimension greater than a horizontal dimension of the integrated circuit device.

### Claim 15 (depends on 14)

The device of claim 14, wherein the patterned conductor includes polysilicon.

### Claim 16 (depends on 14)

The device of claim 14, wherein the insulator includes a buried oxide that is adapted to electrical isolate the patterned conductor from the substrate.

### Claim 17 (depends on 14)

The silicon-on-insulator semiconductor device of claim 14, wherein the different regions are electrically decoupled from the substrate.

### Claim 18

A silicon-on-insulator semiconductor device, comprising:
a substrate configured to include a substrate potential;
an insulator in contact with the substrate;
a recess formed in the insulator, wherein the recess has a depth of about 500 angstroms;
a localized biasing conductor in the recess that is electrically isolated from the substrate;
a silicon layer formed on and in contact with the insulator and the conductor;
at least one integrated circuit device formed in the silicon layer; and
the conductor including a first part being in contact with a first portion of the silicon layer to provide a localized bias to the first portion of the silicon layer that is different than a bias to a second portion of the silicon layer, the first part having a horizontal dimension greater than a horizontal dimension of the first portion of the silicon layer, wherein the first portion and the second portion are configured to receive the different localized bias voltages independent of the substrate potential.

### Claim 19 (depends on 18)

The device of claim 18, wherein the conductor is adapted to provide a bias voltage to the silicon layer.

### Claim 20 (depends on 19)

The device of claim 19, wherein the conductor is adapted to ground the silicon layer.

### Claim 21 (depends on 18)

The device of claim 18, wherein the substrate includes at least one second integrated circuit device, and the insulator is formed on the at least one second integrated circuit device.

### Claim 22 (depends on 21)

The device of claim 21, wherein the at least one second integrated circuit device includes a capacitor.

### Claim 23 (depends on 22)

The device of claim 22, wherein the conductor includes patterned polysilicon.

### Claim 24 (depends on 22)

The device of claim 22, wherein the insulator includes a buried oxide that is adapted to electrical isolate the conductor from the at least one second integrated circuit.

### Claim 25 (depends on 18)

The silicon-on-insulator semiconductor device of claim 18, wherein the first portion, the second portion and the substrate are electrically decoupled.

### Claim 26

A silicon-on-insulator semiconductor device, comprising:
a substrate configured to include a substrate potential;
an insulator in contact with the substrate;
a recess in the insulator;
a localized biasing conductor in the recess that is electrically isolated from the substrate;
a silicon layer formed on and in contact with the insulator and the conductor;
at least one integrated circuit device formed in the silicon layer;
wherein the localized biasing conductor includes a localized biased portion configured to provide a localized bias voltage to the integrated circuit device to adjust a bias potential of the integrated circuit device independent of the substrate potential;
wherein the localized biased portion has a horizontal dimension greater than a horizontal dimension of the integrated circuit device; and
wherein the conductor has a top surface substantially planar with the top surface of the insulator, and the silicon layer being on the top surfaces of both the conductor layer and the insulator layer.

### Claim 27 (depends on 26)

The device of claim 26, wherein the conductor includes polysilicon.

### Claim 28 (depends on 27)

The device of claim 27, wherein the insulator includes a buried oxide that is adapted to electrical isolate the conductor from the substrate.

### Claim 29 (depends on 28)

The device of claim 28, wherein the substrate includes a plurality of integrated circuit devices.

### Claim 30 (depends on 26)

The silicon-on-insulator semiconductor device of claim 26, wherein the integrated circuit device is electrically decoupled from the substrate.

### Claim 31

A silicon-on-insulator semiconductor device, comprising:
a substrate;
an insulator in contact with the substrate;
a recess in the insulator;
a first localized biasing conductor in the recess;
a second localized biasing conductor in the insulator, the second localized biasing conductor providing a bias voltage different than the first localized biasing conductor, wherein the first localized biasing conductor and the second localized biasing conductor are electrically insulated from the substrate;
a silicon layer formed on and in contact with the insulator and the conductor; and
a transistor formed in the silicon layer; wherein the first localized biasing conductor is adapted to provide a bias voltage to the transistor.

### Claim 32 (depends on 31)

The device of claim 31, wherein the transistor that includes a base that is over the first localized biasing conductor.

### Claim 33 (depends on 32)

The device of claim 32, wherein the transistor includes a base in electrical and physical contact with the first localized biasing conductor.

### Claim 34 (depends on 33)

The device of claim 33, wherein the base is a doped silicon.

### Claim 35 (depends on 34)

The device of claim 34, wherein the doped silicon base is doped with a P-type dopant.

### Claim 36 (depends on 31)

The device of claim 31, wherein the recess has a depth of about 500 angstroms.

### Claim 37

A silicon-on-insulator semiconductor device, comprising:
a substrate;
an insulator in contact with the substrate;
a first patterned conductor within the insulator and electrically insulated from the substrate;
a first voltage source connected to the first patterned conductor;
a second patterned conductor within the insulator and electrically insulated from the substrate;
a second voltage source connected to the second patterned conductor;
a silicon layer formed on and in contact with the insulator, the first patterned conductor and the second patterned conductor;
at least one first integrated circuit device formed in the silicon layer; wherein the first patterned conductor is adapted to provide a first bias voltage to the first integrated circuit;
at least second integrated circuit device formed in the silicon layer; wherein the second patterned conductor is adapted to provide a second bias voltage to the second integrated circuit.

### Claim 38 (depends on 37)

The device of claim 37, wherein the first bias voltage is not equal to the second bias voltage.

### Claim 39 (depends on 37)

The device of claim 37, wherein the first bias voltage is less than a ground.

### Claim 40 (depends on 37)

The device of claim 37, wherein the first integrated circuit includes an access transistor for a memory device.

### Claim 41 (depends on 40)

The device of claim 40, wherein the second integrated circuit includes a logic circuit device.

### Claim 42 (depends on 37)

The device of claim 37, wherein the first patterned conductor does not extend to the substrate, and wherein the second patterned conductor within the insulator does not extend to the substrate.

### Claim 43 (depends on 42)

The device of claim 42, wherein the substrate includes a substrate bias voltage that is different than at least one of the first voltage source and the second voltage source.

### Claim 44

An integrated circuit memory device, comprising:
a silicon-on-insulator structure;
an access circuit;
a memory array operably connected to the access circuit;
wherein at least one of the access circuit and the memory cell array is in the silicon-on-insulator structure; and
wherein the silicon on insulator structure includes:
a substrate configured to include a substrate potential;
an insulative layer in contact with the substrate;
a conductor within the insulative layer, the conductor including a local portion to provide a bias signal to the at least one of the access circuit and the memory cell array, the local portion adapted to provide the bias signal to the access circuit and the memory cell array independent of the substrate potential;
a silicon layer on and in contact with the insulative layer and the conductor; and
wherein the local portion has a horizontal dimension greater than a horizontal dimension of an integrated circuit device of the at least one of the access circuit and the memory cell array.

### Claim 45 (depends on 44)

The memory device of claim 44, wherein the memory array includes a DRAM memory array.

### Claim 46 (depends on 44)

The memory device of claim 44, wherein the access circuits includes access transistors that include body regions.

### Claim 47 (depends on 46)

The memory device of claim 46, wherein the conductor is adapted to provide a body bias voltage to the body regions.

### Claim 48 (depends on 47)

The memory device of claim 47, wherein the body bias voltage is less than ground.

### Claim 49 (depends on 47)

The memory device of claim 47, wherein the body bias voltage is about ground.

### Claim 50 (depends on 44)

The integrated circuit memory device of claim 44, wherein the access circuit and the memory cell array are electrically decoupled from the substrate.

### Claim 51

A silicon-on-insulator integrated circuit device, comprising:
a substrate;
an insulator layer in contact with the substrate;
a recess in the insulator layer;
a patterned biasing conductor layer in the recess and electrically insulated from the substrate by the insulator layer;
a silicon layer formed on and in contact with both the insulator layer and at least a portion of the patterned biasing conductor layer;
a body region formed in the silicon layer over the portion of the conductor layer;
a first source/drain region formed in the silicon layer adjacent the body region;
a second source/drain region formed in the silicon layer adjacent the body region and remote the first source/drain region;
a gate formed on the body region intermediate the first source/drain region and the second source/drain region; and
wherein the patterned biasing conductor layer is adapted to provide a first bias voltage to the body region and a second bias voltage to a further portion of the silicon layer.

### Claim 52 (depends on 51)

The device of claim 51, wherein the silicon layer has a thickness to prevent the first source/drain region from electrically communicating with the conductor.

### Claim 53 (depends on 51)

The device of claim 51, wherein the silicon layer has a thickness to prevent the second source/drain region from electrically communicating with the conductor.

### Claim 54 (depends on 51)

The device of claim 51, wherein the conductor is connected to a Vbb source.

### Claim 55 (depends on 51)

The device of claim 51, wherein the conductor is electrically connected to the body region.

### Claim 56

A silicon-on-insulator semiconductor device, comprising:
a substrate;
an insulator in contact with the substrate;
a patterned, voltage-biasing conductor layer within the insulator and electrically insulated from the substrate by the insulator layer;
a silicon layer formed on and in contact with the insulator and the conductor layer; and
the conductor remaining below the silicon layer and being adapted to provide a plurality of bias voltages.

### Claim 57 (depends on 56)

The device of claim 56, wherein the silicon layer includes at least one integrated circuit device formed in the silicon layer.

### Claim 58 (depends on 56)

The device of claim 56, wherein the conductor includes a first portion that is floating.

### Claim 59 (depends on 58)

The device of claim 58, wherein the conductor includes a second portion that is connected to ground.

### Claim 60 (depends on 56)

The device of claim 56, wherein the conductor includes a first portion that is biased to a voltage.

### Claim 61 (depends on 56)

The device of claim 56, wherein the conductor includes a first portion that is biased to a booted voltage.

### Claim 62

A silicon-on-insulator semiconductor device, comprising:
a substrate configured to include a substrate potential;
an insulator in contact with the substrate;
a conductor layer within the insulator, wherein the conductor layer includes a voltage biased, local portion;
a silicon layer formed on and in contact with the insulator and the conductor layer, wherein the silicon layer includes at least one integrated circuit device formed in the silicon layer and is biased by the voltage biased, local portion of the conductor layer, and wherein the voltage biased, local portion is configured to bias the integrated circuit independent of the substrate potential;
a discharge circuit connected to the conductor layer; and
wherein the voltage biased, local portion has a horizontal dimension greater than a horizontal dimension of the biased, integrated circuit device.

### Claim 63 (depends on 62)

The device of claim 62, wherein the discharge circuit includes a capacitor.

### Claim 64 (depends on 62)

The device of claim 62, wherein the at least one integrated circuit device. includes a body, and wherein the capacitor is adapted to draw electrical charge from the body.

### Claim 65 (depends on 64)

The device of claim 64, wherein the discharge circuit includes a switch that connects the capacitor to ground.

### Claim 66 (depends on 62)

The device of claim 62, wherein the discharge circuit includes a capacitor connected to the conductor layer and a transistor connecting the capacitor to ground.

### Claim 67 (depends on 66)

The device of claim 66, wherein the transistor is adapted to periodically discharges the capacitor to ground.

### Claim 68 (depends on 62)

The silicon-on-insulator semiconductor device of claim 62, wherein the integrated circuit is electrically decoupled from the substrate.