# US 7,608,912 B2 · Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,608,912 B2
- Document ID: US7608912B2
- Status: Granted
- Kind: B2
- Application number: 11/422,659
- Filed: 2006-06-07
- Published: 2007-04-05
- Granted: 2009-10-27
- Earliest claimed: 2005-09-30
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Kai Frohberg; Joerg Hohage; Thomas Werner
- Web page: https://patentgrep.com/patent/US7608912B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10P 30/40: into insulating materials
- H10P 50/283: {by chemical means}
- H10P 14/6306: {of the semiconductor materials}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in logic areas by correspondingly providing contact etch stop layers with compressive and tensile stress for P-channel transistors and N-channel transistors in these logic areas. Consequently, a reduced failure rate may be obtained.

## Claims

### Claim 1

A semiconductor device, comprising:
a first device region including a plurality of first P-channel transistors and first N-channel transistors, said first P-channel transistors and said first N-channel transistors forming a first functional block;
a second device region including a plurality of second P-channel transistors and second N-channel transistors, said second P-channel transistors and said second N-channel transistors forming a second functional block;
a first dielectric contact etch stop layer formed in said first device region, said first dielectric contact etch stop layer comprising a plurality of first portions having a first intrinsic stress value and a plurality of second portions having a second intrinsic stress value other than said first intrinsic stress value, said first portions of said first dielectric layer being formed above said first P-channel transistors and said second portions of said first dielectric layer being formed above said first N-channel transistors; and
a second dielectric contact etch stop layer formed in said second device region, said second dielectric contact etch stop layer comprising a plurality of first portions of said second dielectric layer having said first intrinsic stress value and a plurality of second portions of said second dielectric layer having a third intrinsic stress value other than said first and second intrinsic stress values, said first portions of said second dielectric layer being formed above said second P-channel transistors and said second portions of said second dielectric being formed above said second N-channel transistors.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein said first functional block represents a logic circuit and said second functional block represents a memory block.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein said memory block comprises a cache memory.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein said first intrinsic stress is compressive and said second intrinsic stress is tensile.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein an absolute amount of said third intrinsic stress value is less than absolute amounts of said first and second intrinsic stress values.