# US 7,608,910 B2 · Semiconductor ESD device and methods of protecting a semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,910 B2 - Document ID: US7608910B2 - Status: Granted - Kind: B2 - Application number: 11/366,457 - Filed: 2006-03-03 - Published: 2007-02-08 - Granted: 2009-10-27 - Earliest claimed: 2005-08-05 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Hyung-Lae Eun - Web page: https://patentgrep.com/patent/US7608910B2 ## CPC - H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) - H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} - H10W 20/494: {changeable by the use of an external beam, e.g. laser beam or ion beam} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device and methods for protecting a semiconductor device. In an example, the semiconductor device may include a semiconductor substrate including at least one electrostatic discharge (ESD) protection device, at least one metal interconnection line connected to the at least one ESD protection device through a conductive plug and a passivation layer disposed on less than all of the metal interconnection line. In an example method, a semiconductor device may be protected by diverting at least a portion of an electron build-up from an accumulation point to one or more protective circuits along one or more conductive paths, the electron build-up, without the diverting, sufficient to cause an ESD at the accumulation point. In another example, a semiconductor device may be protected by exposing one or more conductive lines to a fuse opening to avoid an ESD by diverting an electron build-up at the fuse opening to one or more ESD protection devices. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate including at least one electrostatic discharge (ESD) protection device; at least one insulating layer disposed on the semiconductor substrate; a fuse part including a plurality of fuses and a fuse protecting layer disposed on the plurality of fuses, the fuse part being disposed on the first insulating layer; at least one metal interconnection line connected to the at least one ESD protection device through a conductive plug; wherein the at least one metal interconnection line and a fuse opening are formed within the at least one insulating layer; a passivation layer disposed on an uppermost metal interconnection line of the at least one metal interconnection line, wherein the passivation layer exposes portions, adjacent to the fuse opening, of the uppermost metal interconnection line; and a device protective layer covering the exposed portions of the uppermost metal interconnection line, the passivation layer, an upper surface of the at least one insulating layer. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the at least one ESD protection device includes at least one of a diode and a transistor. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the plurality of fuses include at least one of polysilicon and metal. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the at least one metal interconnection line includes at least one of tungsten, aluminum and copper. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the at least one metal interconnection line includes a plurality of metal interconnection lines. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein at least two of the plurality of metal interconnection lines are electrically connected with each other and further connected to a first ESD protection device and a second ESD protection device, respectively. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the passivation layer includes silicon nitride. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the device protection layer includes polyimide. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the at least one metal interconnecting line includes a dummy metal pattern connected to the at least one ESD protection device. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the fuse part includes a plurality of dummy fuses connected to the at least one ESD protection device. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein: the fuse protecting layer is disposed only on the plurality of fuses, and an upper surface of the dummy fuses are exposed in the fuse opening. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the at least one metal interconnection line connects to at least one of a lower portion and upper portion of the fuse opening. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the at least one metal interconnection line includes a first metal interconnection line connected to the lower portion and a second metal interconnection line connected to the upper portion. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the second metal interconnection line is a dummy metal pattern. ### Claim 15 (depends on 1) The semiconductor device of claim 1, wherein the device protective layer directly contacts the exposed portions of the uppermost metal interconnection line. ### Claim 16 (depends on 8) The semiconductor device of claim 8, wherein the polyimide is a photosensitive polyimide.