# US 7,608,903 B2 · Image sensor with SOI substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,903 B2 - Document ID: US7608903B2 - Status: Granted - Kind: B2 - Application number: 11/730,892 - Filed: 2007-04-04 - Published: 2007-10-25 - Granted: 2009-10-27 - Earliest claimed: 2005-07-12 - Assignees: Aptina Imaging Corporation - Inventors: Chandra Mouli - Web page: https://patentgrep.com/patent/US7608903B2 ## CPC - H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes} - H10F 39/014: {of CMOS image sensors} - H10F 39/182: {Colour image sensors} - H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements} - H10F 39/807: {Pixel isolation structures} - H10F 39/811: {Interconnections} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract An imager pixel utilizing a silicon-on-insulator substrate, a photodiode in said substrate below the buried oxide, and a dual contact to said photodiode and methods of forming said imager pixel. The photodiode has an increased fill factor due to its increased size relative to the pixel. ## Claims ### Claim 1 An imager pixel, comprising: a silicon-on-insulator substrate comprising a lower substrate portion, a buried oxide over the lower substrate portion, and a silicon layer over the buried oxide; a photodiode in the lower substrate portion, wherein the pixel has an area dimension with respect to the substrate, and the photodiode substantially spans the entire pixel area dimension; a dual contact comprising a first contact plug to the photodiode and a second contact plug extending to the lower substrate portion adjacent the photodiode; and a conductive strap connecting the first contact plug with the second contact plug. ### Claim 2 (depends on 1) The imager pixel of claim 1, wherein the photodiode spans at least 95% of the pixel area dimension. ### Claim 3 (depends on 1) The imager pixel of claim 1, wherein the dual contact extends through the buried oxide layer and the silicon layer over the buried oxide layer. ### Claim 4 (depends on 3) The imager pixel of claim 3, wherein the second contact plug extends through an isolation region to reach the lower substrate. ### Claim 5 (depends on 4) The imager pixel of claim 4, wherein the first contact plug extends through a source/drain region of a pixel transistor. ### Claim 6 (depends on 3) The imager pixel of claim 3, wherein the substrate has a p-type conductivity region around the dual contact. ### Claim 7 (depends on 1) The imager pixel of claim 1, wherein the buried oxide is rich in at least one of boron, fluorine, and deuterium. ### Claim 8 (depends on 1) The imager pixel of claim 1, wherein the lower substrate portion is an n-on-n+ epitaxial material. ### Claim 9 (depends on 8) The imager pixel of claim 8, wherein a lower substrate portion is a graded n+ epi layer. ### Claim 10 (depends on 1) The imager pixel of claim 1, wherein the photodiode is configured to sense light impacting the lower substrate portion on a side thereof opposite the buried oxide and silicon layer. ### Claim 11 (depends on 1) The imager pixel of claim 1, further comprising at least one second photodiode, wherein each of the photodiode and the second photodiode comprises a respective charge collection region, the respective charge collection regions being positioned at respective depths within the substrate relative to a light source such that the photodiode senses a first color of light and the second photodiode senses a second color of light. ### Claim 12 (depends on 1) The imager pixel of claim 1, further comprising at least one second photodiode and at least one third photodiode, wherein each of the photodiode, the second photodiode, and the third photodiode each comprises a respective charge collection region, the respective charge collection regions being positioned at respective depths within the substrate relative to a light source such that the photodiode senses a first color of light, the second photodiode senses a second color of light, and the third photodiode senses a third color of light. ### Claim 13 A CMOS imager, comprising: a silicon-on-insulator substrate comprising a lower substrate portion, a buried oxide over the lower substrate portion, and a silicon layer over the buried oxide; an isolation region in the silicon layer, the isolation region defining a pixel area; a pinned photodiode in the lower substrate portion; a pixel circuit comprising a plurality of transistors supported by the silicon layer; a dual contact from a transfer transistor to a charge collection region of the photodiode, the dual contact having a first contact penetrating the lower substrate portion to the charge collection region and a second contact penetrating the isolation region and lower substrate portion adjacent the photodiode; and a conductive strap connecting the first contact and the second contact of the dual contact. ### Claim 14 (depends on 13) The CMOS imager of claim 13, wherein the first contact extends through a source/drain region of the transfer transistor and the buried oxide to the charge collection region. ### Claim 15 (depends on 13) The CMOS imager of claim 13, wherein the buried oxide is rich in at least one of boron, fluorine, and deuterium. ### Claim 16 (depends on 13) The CMOS imager of claim 13, wherein the photodiode is configured to sense light impacting the lower substrate portion on a side of the lower substrate portion opposite the buried oxide and silicon layer. ### Claim 17 A processor system, comprising: an imager coupled to a processor, the imager comprising an array of pixels, each pixel comprising: a silicon-on-insulator substrate comprising a lower substrate portion, a buried oxide over the lower substrate portion, and a silicon layer over the buried oxide; and a pinned photodiode in the lower substrate portion, wherein the pixel has an area dimension with respect to the substrate and the photodiode substantially spans the entire pixel area dimension; a first contact through the silicon layer and buried oxide to the pinned photodiode; a second contact through the silicon layer and buried oxide to the lower substrate portion outside the pinned photodiode; and a conductive strap connecting the first contact with the second contact. ### Claim 18 (depends on 17) The processor system of claim 17, further comprising a dual contact to the photodiode, wherein a first contact plug extends to the photodiode and a second contact plug extends to a region of the substrate adjacent the photodiode. ### Claim 19 (depends on 17) The processor system of claim 17, further comprising a shallow trench isolation region around the pixel. ### Claim 20 (depends on 17) The processor system of claim 17, further comprising a diffused isolation region around the pixel.