# US 7,608,897 B2 · Sub-surface region with diagonal gap regions

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- Number: US 7,608,897 B2
- Document ID: US7608897B2
- Status: Granted
- Kind: B2
- Application number: 12/011,665
- Filed: 2008-01-28
- Published: 2008-05-29
- Granted: 2009-10-27
- Earliest claimed: 2002-12-31
- Inventors: Mike Pelham; James B. Burr
- Web page: https://patentgrep.com/patent/US7608897B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D 89/10: Integrated device layouts
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

## Claims

### Claim 1

A semiconductor device comprising:
a surface;
a plurality of surface wells of a first conductivity formed below the surface; and
a sub-surface layer of the first conductivity formed below the surface wells and electrically coupled to the surface wells, wherein the sub-surface layer comprises gap regions oriented diagonally with respect to an orientation of the surface wells.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the sub-surface layer has an N-type doping.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the surface wells have an N-type doping.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the sub-surface layer has a P-type doping.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the surface wells have a P-type doping.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).

### Claim 8

A semiconductor device comprising:
a surface;
a first surface well of a first conductivity formed below the surface;
a second surface well of the first conductivity formed below the surface;
a region of a second conductivity below the surface and between the first surface well and the second surface well; and
a sub-surface layer of the first conductivity formed below the first and second surface wells and below the region and electrically coupled to the first and second surface wells, wherein the sub-surface layer comprises gap regions oriented diagonally with respect to an orientation of the first and second surface wells without isolating the region.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the sub-surface layer has an N-type doping.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the surface wells have an N-type doping and wherein the region has a P-type doping.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the sub-surface layer has a P-type doping.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the surface wells have a P-type doping and wherein the region has a N-type doping.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).

### Claim 15

A semiconductor device comprising:
a surface;
a first surface well of a first conductivity formed below the surface;
a second surface well of the first conductivity formed below the surface; and
a sub-surface mesh structure of the first conductivity formed below the first and second surface wells and electrically coupled to the first and second surface wells, wherein the sub-surface mesh structure is oriented diagonally with respect to an orientation of the first and second surface wells.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the sub-surface mesh structure has an N-type doping.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the surface wells have an N-type doping.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the sub-surface mesh structure has a P-type doping.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the surface wells have a P-type doping, and
wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).