# US 7,608,895 B2 · Modular CMOS analog integrated circuit and power technology

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- Number: US 7,608,895 B2
- Document ID: US7608895B2
- Status: Granted
- Kind: B2
- Application number: 11/881,841
- Filed: 2007-07-30
- Published: 2007-11-29
- Granted: 2009-10-27
- Earliest claimed: 2002-09-29
- Assignees: Advanced Analogic Technologies, Inc.; Advanced Analogic Technologies (Hong Kong) Limited
- Inventors: Richard K. Williams; Michael E. Cornell; Wai Tien Chen
- Web page: https://patentgrep.com/patent/US7608895B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 10/421: {having both emitter-base and base-collector junctions ending at the same surface of the body}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/0121: {the complementary BJTs being vertical BJTs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/212: {Through-implantation}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10W 10/0126: {introducing electrical active impurities in local oxidation regions to create channel stoppers}
- H10W 10/0127: {using both n-type and p-type impurities, e.g. for isolation of complementary doped regions}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 15/00: Highly-doped buried regions of integrated devices
- H10W 15/01: {Manufacture or treatment}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 64/511: {for IGFETs}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

## Claims

### Claim 1

An isolated NMOS structure formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said isolated NMOS structure comprising an NMOS transistor and an isolation structure;
said NMOS transistor comprising:
a P well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions of said P well underlying a field oxide layer, said relatively deep central portion of said P well underlying an opening in said field oxide layer;
a gate overlying a channel region of said P well and separated from said substrate by a gate oxide layer;
an N-type source region located at the surface of said substrate on one side of said gate;
an N-type drain region located at the surface of said substrate on an opposite side of said gate from said N-type source region, said N-type drain region having a breakdown voltage relative to said P well; and
electrical contacts to said gate, N-type source region, N-type drain region and P well of said NMOS;
wherein said P well comprises an implanted P layer, said P layer comprising a deep section in said central portion of said P well, shallow sections in said side portions of said P well, and transition sections connecting said deep section and said shallow sections of said P layer, each vertical cross-section of said P layer comprising a location of peak doping concentration; said locations of peak doping concentration being relatively deep in said substrate in said deep section of said P layer and being at a shallower level in said substrate in said shallow sections of said P layer, the doping concentration of said P well at said surface of said substrate in said side sections of said P well being higher than the doping concentration of said P well at said surface of said substrate in said central portion of said P well;
said isolation structure comprising:
an N well extending downward from the surface of said substrate and laterally surrounding said P well;
an N-type isolation layer located in said substrate and underlying said P well, said N-type isolation layer extending laterally beyond said P well a sufficient distance and said N well being sufficiently deep in said substrate such that said N-type isolation layer overlaps said N well so as to isolate said P well from said P-type substrate; and
an electrical contact to said N well.

### Claim 2 (depends on 1)

The isolated NMOS structure of claim 1 wherein said isolation structure is biased at a positive voltage with respect to said substrate.

### Claim 3 (depends on 2)

The isolated NMOS structure of claim 2 wherein said positive voltage does not exceed a breakdown voltage of said isolation structure relative to said substrate.

### Claim 4 (depends on 1)

The isolated NMOS structure of claim 1 wherein, in plan view, said N well has an annular shape.

### Claim 5 (depends on 1)

The isolated NMOS structure of claim 1 wherein, in plan view, said N well and N-type isolation layer appear as overlapping geometric shapes, the geometric shape of said N well being annular and surrounding an open central area, said open central area containing said P well.

### Claim 6 (depends on 5)

The isolated NMOS structure of claim 5 wherein said geometric shape of each of said N well and said N-type isolation layer is rectangular.

### Claim 7 (depends on 1)

The isolated NMOS structure of claim 1 wherein said P well is biased to the same electrical potential as said isolation structure.

### Claim 8

An isolated CMOS arrangement of transistors formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said CMOS arrangement comprising an isolated CMOS pair, said CMOS pair comprising a PMOS and a NMOS, and an associated isolation structure:
said PMOS comprising:
an N well having a relatively deep central portion and relatively shallow side portions, said side portions of said N well underlying a field oxide layer, said central portion of said N well underlying a first opening in said field oxide layer;
a first gate overlying a channel region of said N well and separated from said substrate by a first gate oxide layer;
a P-type source region located at the surface of said substrate on one side of said first gate; and
a P-type drain region located at the surface of said substrate on an opposite side of said first gate from said P-type source region;
electrical contacts to said first gate, P-type source region, P-type drain region and N well;
said NMOS comprising:
a P well having a relatively deep central portion and relatively shallow side portions, said relatively shallow side portions of said P well underlying the field oxide layer, said relatively deep central portion of said P well underlying a second opening in said field oxide layer, said P well being electrically isolated from the surrounding P-type substrate by said isolation structure;
a second gate overlying a channel region of said P well and separated from said substrate by a second gate oxide layer;
an N-type source region located at the surface of said substrate on one side of said second gate; and
an N-type drain region located at the surface of said substrate on an opposite side of said second gate from said N-type source region;
electrical contacts to said second gate, N-type source region, N-type drain region and P well;
said isolation structure comprising:
said N well, said N well extending downward from the surface of said substrate and laterally surrounding said P well; and
an N-type isolation layer located in said substrate and underlying said P well and at least a portion of said N well, said N-type isolation layer extending laterally beyond said P well a sufficient distance and said second N well being sufficiently deep in said substrate such that said N-type isolation layer overlaps said N well so as to isolate said P well from said P-type substrate.

### Claim 9 (depends on 8)

The isolated CMOS arrangement of claim 8 wherein:
a first doping concentration profile taken at a vertical cross-section through said central portion of said N well is non-monotonic, said first doping concentration profile having a peak doping concentration located a first distance below said surface of said substrate;
a second doping concentration profile taken at a vertical cross-section through one of said side portions of said N well has a peak doping concentration located at or a second distance below said surface of said substrate, said second distance being less than said first distance; and
a doping concentration at said surface of said substrate in said side portion of said N well is greater than a doping concentration at said surface of said substrate in said central portion of said N well.

### Claim 10 (depends on 8)

The isolated CMOS arrangement of claim 8 wherein:
a first doping concentration profile taken at a vertical cross-section through said central portion of said P well is non-monotonic, said first doping concentration profile having a peak doping concentration located a first distance below said surface of said substrate;
a second doping concentration profile taken at a vertical cross-section through one of said side portions of said P well has a peak doping concentration located at or a second distance below said surface of said substrate, said second distance being less than said first distance; and
a doping concentration at said surface of said substrate in said side portion of said P well is greater than a doping concentration at said surface of said substrate in said central portion of said N well.

### Claim 11 (depends on 8)

The isolated CMOS arrangement of claim 8 wherein said N-type isolation layer underlies all of said N well and all of said P well.

### Claim 12 (depends on 11)

The isolated CMOS arrangement of claim 11 wherein said N well and said P well are separated by a gap and said N-type isolation layer underlies said gap.

### Claim 13 (depends on 8)

The isolated CMOS arrangement of claim 8 wherein said N-type isolation layer has a relatively deep portions under said first and second openings in said field oxide layer and relatively shallow portions under said field oxide layer.

### Claim 14 (depends on 8)

The isolated CMOS arrangement of claim 8 wherein said N-type isolation layer has a uniform depth in the substrate.

### Claim 15

A CMOS arrangement of transistors formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said CMOS arrangement comprising a CMOS pair, said CMOS pair comprising a PMOS and a NMOS:
said PMOS comprising:
an N well having a relatively deep central portion and relatively shallow side portions, said side portions of said N well underlying a field oxide layer, said central portion of said N well underlying a first opening in said field oxide layer;
a first gate overlying a channel region of said N well and separated from said substrate by a first gate oxide layer;
a P-type source region located at the surface of said substrate on one side of said first gate; and
a P-type drain region located at the surface of said substrate on an opposite side of said first gate from said P-type source region, said P-type drain region being laterally separated from said channel region of said N well by a P-type drain extension, said P-type drain extension being located at said surface of said substrate, said P-type drain extension having a doping concentration less than a doping concentration of said P-type drain region;
said NMOS comprising:
a P well having a relatively deep central portion and relatively shallow side portions, said side portions of said P well underlying the field oxide layer, said central portion of said P well underlying a second opening in said field oxide layer;
a second gate overlying a channel region of said P well and separated from said substrate by a second gate oxide layer;
an N-type source region located at the surface of said substrate on one side of said second gate; and
an N-type drain region located at the surface of said substrate on an opposite side of said second gate from said N-type source region, said N-type drain region being laterally separated from said channel region of said P well by an N-type drain extension, said N-type drain extension being located at said surface of said substrate, said N-type drain extension having a doping concentration less than a doping concentration of said N-type drain region;
wherein said P well comprises a second N-type drain extension, said second N-type drain extension being located at said surface of said substrate and extending between said N-type drain region and said field oxide layer.

### Claim 16 (depends on 15)

The CMOS arrangement of claim 15 wherein said N well comprises a second P-type drain extension, said second P-type drain extension being located at said surface of said substrate and extending between said P-type drain region and said field oxide layer.

### Claim 17

A CMOS arrangement of transistors formed in a semiconductor substrate, said substrate being doped with P-type impurity and not comprising an epitaxial layer, said CMOS arrangement comprising a CMOS pair, said CMOS pair comprising a PMOS and a NMOS:
said PMOS comprising:
an N well having a relatively deep central portion and relatively shallow side portions, said side portions of said N well underlying a field oxide layer, said central portion of said N well underlying a first opening in said field oxide layer;
a first gate overlying a channel region of said N well and separated from said substrate by a first gate oxide layer;
a P-type source region located at the surface of said substrate on one side of said first gate; and
a P-type drain region located at the surface of said substrate on an opposite side of said first gate from said P-type source region, said P-type drain region being laterally separated from said channel region of said N well by a P-type drain extension, said P-type drain extension being located at said surface of said substrate, said P-type drain extension having a doping concentration less than a doping concentration of said P-type drain region;
said NMOS comprising:
a P well having a relatively deep central portion and relatively shallow side portions, said side portions of said P well underlying the field oxide layer, said central portion of said P well underlying a second opening in said field oxide layer;
a second gate overlying a channel region of said P well and separated from said substrate by a second gate oxide layer;
an N-type source region located at the surface of said substrate on one side of said second gate; and
an N-type drain region located at the surface of said substrate on an opposite side of said second gate from said N-type source region, said N-type drain region being laterally separated from said channel region of said P well by an N-type drain extension, said N-type drain extension being located at said surface of said substrate, said N-type drain extension having a doping concentration less than a doping concentration of said N-type drain region;
said CMOS arrangement further comprising a relatively heavily doped N-type guard ring in said side portion of said N well, said N-type guard ring laterally surrounding said central portion of said N well.

### Claim 18 (depends on 17)

The CMOS arrangement of claim 17 wherein said N-type guard ring is located beneath said field oxide layer and is spaced apart from said first opening in said field oxide layer.

### Claim 19 (depends on 17)

The CMOS arrangement of claim 17 comprising a relatively heavily doped P-type guard ring in said side portion of said P well, said P-type guard ring laterally surrounding said central portion of said P well.