# US 7,608,893 B2 · Multi-channel transistor structure and method of making thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,893 B2 - Document ID: US7608893B2 - Status: Granted - Kind: B2 - Application number: 12/037,147 - Filed: 2008-02-26 - Published: 2008-06-19 - Granted: 2009-10-27 - Earliest claimed: 2005-08-08 - Assignees: Freescale Semiconductor, Inc. - Inventors: Marius Orlowski - Web page: https://patentgrep.com/patent/US7608893B2 ## CPC - H10D 62/221: {of FETs} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/121: {oriented parallel to substrates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain. ## Claims ### Claim 1 An electronic device comprising: a first current electrode; a second current electrode; a first channel coupled to the first current electrode and the second current electrode, and surrounded by a gate electrode in a first plane, wherein the first plane is perpendicular to a major surface of a substrate over which the first channel lies; and a second channel coupled to the first current electrode and the second current electrode, and surrounded by the gate electrode in the first plane, wherein the second channel is substantially parallel to the first channel within a second plane, wherein the second plane is parallel to the major surface. ### Claim 2 (depends on 1) The electronic device of claim 1, wherein the device further comprises a third channel coupled to the first current electrode and the second current electrode and surrounded by the gate electrode in the first plane, wherein the third channel is substantially parallel to the first channel within a third plane, wherein the third plane is perpendicular to the major surface. ### Claim 3 (depends on 2) The electronic device of claim 2, wherein a composition of the first channel and a composition of the third channel each comprise a semiconductor. ### Claim 4 (depends on 3) The electronic device of claim 3, wherein the composition of the first channel and a composition of the third channel are the same. ### Claim 5 (depends on 3) The electronic device of claim 3, wherein the composition of the first channel and a composition of the third channel are different. ### Claim 6 (depends on 2) The electronic device of claim 2, wherein the device further comprises a fourth channel coupled to the first current electrode and the second current electrode and surrounded by the gate electrode in the first plane, wherein the fourth channel is substantially parallel to the third channel within a fourth plane, wherein the fourth plane is parallel to the major surface. ### Claim 7 (depends on 6) The electronic device of claim 6, wherein a composition of the third channel and a composition of the fourth channel each comprise a semiconductor. ### Claim 8 (depends on 7) The electronic device of claim 7, wherein the composition of the first channel and a composition of the third channel are the same. ### Claim 9 (depends on 8) The electronic device of claim 8, wherein a composition of the first channel and a composition comprises a semiconductor. ### Claim 10 (depends on 9) The electronic device of claim 9, wherein the composition of the first channel and a composition of the third channel are the same. ### Claim 11 (depends on 9) The electronic device of claim 9, wherein the composition of the first channel and a composition of the third channel are different. ### Claim 12 (depends on 1) The electronic device of claim 1, wherein a composition of the first channel and a composition of the second channel each comprise a semiconductor. ### Claim 13 (depends on 12) The electronic device of claim 12, wherein the composition of the first channel and a composition of the third channel are the same. ### Claim 14 (depends on 1) The electronic device of claim 1, wherein a diameter of the first channel in the first plane is less than approximately 30 nanometers. ### Claim 15 (depends on 14) The electronic device of claim 14, wherein a diameter of the first channel in the first plane is less than approximately 15 nanometers. ### Claim 16 (depends on 15) The electronic device of claim 15, wherein a diameter of the first channel in the first plane is less than approximately 5.0 nanometers. ### Claim 17 (depends on 1) The electronic device of claim 1 further comprising a first dielectric region disposed between the first channel and the gate electrode, the first dielectric region surrounding the first channel in the first plane. ### Claim 18 (depends on 17) The electronic device of claim 17 further comprising a second dielectric region disposed between the second channel and the gate electrode, the second dielectric region surrounding the first channel in the first plane. ### Claim 19 (depends on 17) The electronic device of claim 17, wherein a diameter of the first channel in the first plane is less than approximately 30 nanometers. ### Claim 20 (depends on 19) The electronic device of claim 19, wherein a diameter of the second channel in the first plane is less than approximately 30 nanometers.