# US 7,608,889 B2 · Lateral diffusion metal-oxide-semiconductor structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,608,889 B2
- Document ID: US7608889B2
- Status: Granted
- Kind: B2
- Application number: 11/864,278
- Filed: 2007-09-28
- Published: 2009-04-02
- Granted: 2009-10-27
- Earliest claimed: 2007-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Dah-Chuen Ho; Chien-Shao Tang; Zhe-Yi Wang; Yu-Chang Jong
- Web page: https://patentgrep.com/patent/US7608889B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.

## Claims

### Claim 1

A lateral diffusion metal-oxide-semiconductor (LDMOS) structure, comprising:
a gate formed on a semiconductor substrate;
a source formed in the semiconductor substrate;
a drain formed in the semiconductor substrate;
a shallow trench isolation formed in the semiconductor substrate and between the drain and the gate, wherein a top surface of the shallow trench isolation is lower than a top surface of the semiconductor substrate; and
a step disposed between the top surface of the shallow trench isolation and the top surface of the semiconductor substrate.

### Claim 2 (depends on 1)

The LDMOS structure in accordance with claim 1, wherein the top surface of the shallow trench isolation is lower than the top surface of the semiconductor substrate by 300-1500 angstroms.

### Claim 3 (depends on 1)

The LDMOS structure in accordance with claim 1, wherein the gate comprises polysilicon.

### Claim 4 (depends on 1)

The LDMOS structure in accordance with claim 1, further comprising an oxide layer interposed between the gate and the top surface of the shallow trench isolation.

### Claim 5 (depends on 1)

The LDMOS structure in accordance with claim 1, wherein the shallow trench isolation is used to withstand high voltages applied to the drain.

### Claim 6 (depends on 1)

The LDMOS structure in accordance with claim 1, wherein the gate comprises a bottom surface on the top surface of the shallow trench isolation, and the bottom surface of the gate on the top surface of the shallow trench isolation is lower than the top surface of the semiconductor substrate.

### Claim 7 (depends on 6)

The LDMOS structure in accordance with claim 6, wherein the bottom surface of the gate on the top surface of the shallow trench isolation is lower than the top surface of the semiconductor substrate by 300-1500 angstroms.

### Claim 8

A LDMOS structure, comprising:
a source formed in a semiconductor substrate;
a drain formed in the semiconductor substrate;
a gate comprising a bottom surface; and
a shallow trench isolation formed in the semiconductor substrate and between the drain and the source, wherein the shallow trench isolation comprises a top surface lower than a top surface of the semiconductor substrate;
wherein the gate comprises a first portion on the top surface of the shallow trench isolation and a second portion on the top surface of the semiconductor substrate, and wherein the bottom surface of the first portion of the gate is lower than the top surface of the semiconductor substrate.

### Claim 9 (depends on 8)

The LDMOS structure in accordance with claim 8, wherein the bottom surface of the first portion of the gate is lower than the top surface of the semiconductor substrate by 300-1500 angstroms.

### Claim 10 (depends on 8)

The LDMOS structure in accordance with claim 8, wherein the gate comprises polysilicon.

### Claim 11 (depends on 8)

The LDMOS structure in accordance with claim 8, further comprising an oxide layer underlying the gate.

### Claim 12 (depends on 8)

The LDMOS structure in accordance with claim 8, wherein the shallow trench isolation is used to withstand high voltages applied to the drain.

### Claim 13 (depends on 8)

The LDMOS structure in accordance with claim 8, wherein the top surface of the shallow trench isolation is flat.

### Claim 14 (depends on 13)

The LDMOS structure in accordance with claim 13, wherein the top surface of the shallow trench isolation is lower than the top surface of the semiconductor substrate by 300-1500 angstroms.

### Claim 15

A LDMOS structure, comprising:
a source formed in a semiconductor substrate;
a drain formed in the semiconductor substrate;
a gate; and
a shallow trench isolation formed in the semiconductor substrate and between the drain and the source, and the shallow trench isolation having a top surface below a top surface of the semiconductor substrate; and
wherein the gate extends over a step between the top surface of the isolation structure and the top surface of the semiconductor substrate.

### Claim 16 (depends on 15)

The LDMOS structure in accordance with claim 15, wherein the step is between 300-1500 angstroms.

### Claim 17 (depends on 15)

The LDMOS structure in accordance with claim 15, wherein the gate comprises polysilicon.

### Claim 18 (depends on 15)

The LDMOS structure in accordance with claim 15, further comprising an oxide layer underlying the gate.

### Claim 19 (depends on 15)

The LDMOS structure in accordance with claim 15, wherein the top surface of the shallow trench isolation is flat.

### Claim 20 (depends on 19)

The LDMOS structure in accordance with claim 19, wherein the top surface of the shallow trench isolation is lower than the top surface of the semiconductor substrate by 300-1500 angstroms.