# US 7,608,886 B2 · Systems and methods for a high density, compact memory array

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- Number: US 7,608,886 B2
- Document ID: US7608886B2
- Status: Granted
- Kind: B2
- Application number: 11/327,792
- Filed: 2006-01-06
- Published: 2007-07-12
- Granted: 2009-10-27
- Earliest claimed: 2006-01-06
- Assignees: Macronix International Co., Ltd.
- Inventors: Tzu-Hsuan Hsu; Ming-Hsiu Lee; Chao-I Wu; Ming-Chang Kuo
- Web page: https://patentgrep.com/patent/US7608886B2

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C 16/0475: {comprising two or more independent storage sites which store independent data}
- H10B 43/30: characterised by the memory core region
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

## Claims

### Claim 1

A memory array, comprising:
a first vertical memory cell comprising a first plurality of transistor structures;
a second vertical memory cell comprising a second plurality of transistor structures;
a joint drain region between the first and second memory cells;
a common source region between the first and the second memory cells; and
a joint body region between the first memory cell and the second memory cell,
wherein each of the first plurality of transistor structures share a first common conductive gate region wholly disposed above the common source region.

### Claim 2 (depends on 1)

The memory array of claim 1, further comprising a charge trapping layer, wherein each of the first and second plurality of transistor structures is configured to store two bits of data.

### Claim 3 (depends on 1)

The memory array of claim 1, wherein multi level charge techniques are used to store a plurality of bits of data in each of the first and second plurality of transistor structures.

### Claim 4 (depends on 1)

The memory array of claim 1, wherein each of the first and second plurality of transistor structures are SONOS transistor structures.

### Claim 5 (depends on 1)

The memory array of claim 1, further comprising a charge trapping layer, wherein the first and second vertical memory cells are configured to store 4 bits of data per cell.

### Claim 6 (depends on 1)

The memory array of claim 1, wherein each of the first plurality of transistor structures of the first vertical memory cell include:
the first conductive gate region;
a first drain region;
a body region;
a source region; and
a charge trapping structure.

### Claim 7 (depends on 6)

The memory array of claim 6, wherein the charge trapping structure includes a first dielectric layer, a charge trapping layer, a second dielectric layer.

### Claim 8 (depends on 6)

The memory array of claim 6, wherein the charge trapping structure comprises at least one of nitride, Al2O3, HfO2, or CeO2.

### Claim 9 (depends on 6)

The memory array of claim 6, wherein the charge trapping structure comprises a dielectric material.

### Claim 10 (depends on 6)

The memory array of claim 6, wherein each of the second plurality of transistor structures of the second memory cell include:
a second conductive gate region;
the joint drain region;
the joint body region;
a source region; and
a second trapping layer.

### Claim 11 (depends on 10)

The memory array of claim 10, wherein the second trapping layer comprises an oxide-nitride-oxide layer.

### Claim 12 (depends on 10)

The memory array of claim 10, wherein the second trapping layer comprises at least one of nitride, Al2O3, HfO2, or CeO2.

### Claim 13 (depends on 10)

The memory array of claim 10, wherein the second trapping layer comprises a dielectric material.

### Claim 14 (depends on 10)

The memory array of claim 10, wherein each of the second plurality of transistor structures of the second vertical memory cell include:
a second conductive gate region;
the joint drain region;
the joint body region;
a source region; and
a third trapping layer.

### Claim 15 (depends on 14)

The memory array of claim 14, wherein the third trapping layer comprises an oxide nitride oxide layer.

### Claim 16 (depends on 14)

The memory array of claim 14, wherein the third trapping layer comprises at least one of nitride, Al2O3, HfO2, or CeO2.

### Claim 17 (depends on 14)

The memory array of claim 14, wherein the third trapping layer comprises a dielectric material.

### Claim 18 (depends on 14)

The memory array of claim 14, wherein each of the second plurality of transistor structures of the second memory cell include:
the second conductive gate region;
a second drain region;
a second body region;
a source region; and
a fourth trapping layer.

### Claim 19 (depends on 18)

The memory array of claim 18, wherein the fourth trapping layer comprises an oxide-nitride-oxide layer.

### Claim 20 (depends on 18)

The memory array of claim 18, wherein the fourth trapping layer comprises at least one of nitride, Al2O3, HfO2, or CeO2.

### Claim 21 (depends on 18)

The memory array of claim 18, wherein the fourth trapping layer comprises a dielectric material.

### Claim 22 (depends on 1)

The memory array of claim 1, wherein the first and second plurality of transistor structures are configured to be programmed using a channel hot electron technique.

### Claim 23 (depends on 1)

The memory array of claim 1, wherein the first and second plurality of transistor structures are configured to be erased using a band to band hot hole technique.

### Claim 24 (depends on 1)

The memory array of claim 1, wherein the first and second plurality of transistor structures are configured to be block erased using a Fowler-Nordheim technique.

### Claim 25 (depends on 1)

The memory array of claim 1, wherein each of the second plurality of transistor structures share a second common conductive gate region.

### Claim 26 (depends on 1)

The memory array of claim 1, wherein the first plurality of transistor structures and the second plurality of transistor structures exclude floating gate structures.

### Claim 27 (depends on 1)

The memory array of claim 1, wherein the joint drain region extends above the first common conductive gate region.

### Claim 28

A memory array, comprising:
a first vertical memory cell comprising a first plurality of transistor structures;
a second vertical memory cell comprising a second plurality of transistor structures;
a joint drain region between the first and second memory cells;
a joint body region between the first memory cell and the second memory cell;
a joint source region between the first memory cell and the second memory cell; and
a word line that runs substantially parallel with the joint body region,
wherein each of the first plurality of transistor structures share a first common conductive gate region disposed wholly above the joint source region.

### Claim 29 (depends on 28)

The memory array of claim 28, wherein each of the second plurality of transistor structures share a second common conductive gate region.

### Claim 30 (depends on 28)

The memory array of claim 28, wherein the first plurality of transistor structures and the second plurality of transistor structures exclude floating gate structures.

### Claim 31 (depends on 28)

The memory array of claim 28, wherein the joint drain region extends above the first common conductive gate region.