# US 7,608,884 B2 · Scalable split-gate flash memory cell with high source-coupling ratio

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- Number: US 7,608,884 B2
- Document ID: US7608884B2
- Status: Granted
- Kind: B2
- Application number: 11/088,492
- Filed: 2005-03-24
- Published: 2006-09-28
- Granted: 2009-10-27
- Earliest claimed: 2005-03-24
- Assignees: Taiwan Semiconductor Manufactruing Co., Ltd.
- Inventors: Te-Hsun Hsu; Hung-Cheng Sung
- Web page: https://patentgrep.com/patent/US7608884B2

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A system and method provides an improved source-coupling ratio in flash memories. In one embodiment, a flash memory cell system with high source-coupling ratio includes at least a conventional floating gate device having a floating gate, a drain and a source. The floating gate is formed over a first junction for charging the floating gate by electron injection from the source to the floating gate and at least a first dielectric is layered on top of the floating gate to form a second junction. At least a first polycrystalline silicon is layered on top of the first dielectric, the first polycrystalline silicon electrically connected to the source. Electron tunneling provided through the second junction to the floating gate charges the floating gate, thereby increasing the source-coupling ratio of the floating gate and increasing the efficiency of storing electrical charge.

## Claims

### Claim 1

A flash memory cell system, comprising:
a first floating gate formed on a floating gate dielectric layer and disposed between a first drain and a source;
a source gate dielectric layer formed on the first floating gate;
a first source gate formed on the source gate dielectric layer;
a first dielectric layer formed on the first source gate;
a first high temperature oxide layer disposed on the first dielectric layer;
a source polycrystalline silicon plug disposed on the source and separated from the first floating gate by the first high temperature oxide layer, wherein the source polycrystalline silicon plug is connected to the source and the first source gate to boost electron injections to the first floating gate; and
a first control gate disposed laterally adjacent the first floating gate and the first source gate with the first high temperature oxide layer disposed vertically therebetween.

### Claim 2 (depends on 1)

The system of claim 1, wherein the first dielectric layer comprises a tetraethylorthosilane (TEOS) oxide layer formed on the first source gate.

### Claim 3 (depends on 1)

The system of claim 1, wherein the floating gate dielectric layer is an oxide, or an oxide-nitride-oxide film.

### Claim 4 (depends on 1)

The system of claim 1, wherein the source gate dielectric layer is an oxide film.

### Claim 5 (depends on 1)

The system of claim 1, wherein the first floating gate is formed over a substrate, the source polycrystalline silicon plug is electrically coupled to the source, the source and the first drain are each formed within the substrate and the floating gate dielectric layer is disposed between the first floating gate and a channel formed within the substrate between the first drain and the source.

### Claim 6 (depends on 5)

The system of claim 5, wherein an intersection between the channel and the source is disposed beneath a lateral edge of the first floating gate.

### Claim 7 (depends on 1)

The system of claim 1, wherein contact portions of the source polycrystalline silicon plug include a silicide formed thereon.

### Claim 8 (depends on 1)

The system of claim 1, wherein the first floating gate stores electrical charges injected from the source through the source gate dielectric layer and the floating gate dielectric layer.

### Claim 9 (depends on 1)

The system of claim 1, wherein a channel is formed within a substrate and an intersection between the source and the channel is formed beneath an edge of the first floating gate.

### Claim 10 (depends on 1)

The system of claim 1, wherein the first control gate controls a charging and discharging of the first floating gate.

### Claim 11 (depends on 1)

The system of claim 1, further comprising:
one or more conductive vias coupled to a self-aligned silicide disposed on the first drain for connecting to other electrical circuits; and
one or more sidewall spacers disposed between the one or more conductive vias and the first control gate.

### Claim 12

A non-volatile memory device, comprising:
a first floating gate formed on a floating gate dielectric layer and disposed between a first drain and a source;
a second floating gate formed on the floating gate dielectric layer and disposed between a second drain and the source;
a source gate dielectric layer formed on the first and second floating gates;
a first source gate and a second source gate formed on the source gate dielectric layer;
a first dielectric layer and a second dielectric layer formed on the first and second source gates, respectively;
a first high temperature oxide and a second high temperature oxide formed on the first and second dielectric layers, respectively;
a source polycrystalline silicon plug formed on the source and separated from the first floating gate and the second floating gate by the first and second high temperature oxide layers, respectively, wherein the source polycrystalline silicon plug is connected to the source, the first source gate, and the second source gate to boost electron injections to the first and second floating gates; and
a first control gate disposed laterally adjacent the first floating gate and the first source gate with the first high temperature oxide layer disposed vertically therebetween;
a second control gate disposed laterally adjacent the second floating gate and the second source gate with the second high temperature oxide layer disposed vertically therebetween.

### Claim 13 (depends on 12)

The device of claim 12, wherein the first and second dielectric layers further comprise a tetraethylorthosilane (TEOS) oxide layer formed on the first and second source gates.

### Claim 14 (depends on 12)

The device of claim 12, wherein the floating gate dielectric layer is an oxide, or an oxide-nitride-oxide film.

### Claim 15 (depends on 12)

The device of claim 12, wherein the source gate dielectric layer is an oxide film.

### Claim 16 (depends on 12)

The device of claim 12, wherein the first and second floating gates are formed over a substrate, the source polycrystalline silicon plug is electrically coupled to the source, the source, the first drain, and the second drain are each formed within the substrate and the floating gate dielectric layer is disposed between the first floating gate and a channel formed within the substrate between the first drain and the source.

### Claim 17 (depends on 12)

The device of claim 12, wherein contact portions of the source polycrystalline silicon plug include a silicide formed thereon.

### Claim 18 (depends on 12)

The device of claim 12, wherein the first and second floating gates store electrical charges injected from the source through the source gate dielectric layer and the floating gate dielectric layer.

### Claim 19 (depends on 12)

The device of claim 12, wherein the first and second control gates control a charging and discharging of the first and second floating gates, respectively.