# US 7,608,883 B2 · Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric

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- Number: US 7,608,883 B2
- Document ID: US7608883B2
- Status: Granted
- Kind: B2
- Application number: 12/072,971
- Filed: 2008-02-28
- Published: 2008-06-26
- Granted: 2009-10-27
- Earliest claimed: 2005-11-21
- Assignees: Intel Corporation
- Inventors: Marko Radosavljevic; Amlan Majumdar; Suman Datta; Justin Brask; Brian Doyle; Robert Chau
- Web page: https://patentgrep.com/patent/US7608883B2

## CPC

- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate}
- G11C 2213/17: Memory cell being a nanowire transistor
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10K 85/221: {Carbon nanotubes}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

## Claims

### Claim 1

A method, comprising:
altering a threshold voltage of a transistor by creating a tunneling current that flows through dielectric material located between a quantum dot and into a layer of conductive material, said quantum dot disposed in said dielectric material and located between a carbon nanotube and said layer of conductive material, said transistor having said carbon nanotube electrically coupled between source and drain electrodes, said layer of conductive material forming at least part of said transistor's gate, wherein said electron tunneling current is substantially greater than second tunneling current, if any, between said quantum dot and said carbon nanotube.

### Claim 2 (depends on 1)

The method of claim 1 wherein said tunneling current flows from said quantum dot into said conductive layer.

### Claim 3 (depends on 1)

The method of claim 1 wherein said tunneling current causes said carbon nanotube to induce electrons into a conduction band of said carbon nanotube.

### Claim 4 (depends on 1)

The method of claim 1 wherein said method comprises applying a read voltage at said conductive layer and determining a logical state held by said transistor that is a function of said threshold voltage.

### Claim 5 (depends on 1)

The method of claim 1 wherein said tunneling current flows from said conductive layer and into said quantum dot.

### Claim 6 (depends on 1)

The method of claim 1 wherein said tunneling causes said carbon nanotube to induce holes into a valence band of said carbon nanotube.