# US 7,608,882 B2 · Split-gate non-volatile memory

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- Number: US 7,608,882 B2
- Document ID: US7608882B2
- Status: Granted
- Kind: B2
- Application number: 10/604,692
- Filed: 2003-08-11
- Published: 2005-02-17
- Granted: 2009-10-27
- Earliest claimed: 2003-08-11
- Assignees: Macronix International Co., Ltd.
- Inventors: Hsiang-Lan Lung; Rui-Chen Liu
- Web page: https://patentgrep.com/patent/US7608882B2

## CPC

- H10B 43/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/511: {for IGFETs}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A split-gate non-volatile memory cell is described, including a substrate, a charge-trapping layer on the substrate, a split gate on the charge-trapping layer, and a source/drain in the substrate beside the split gate. The split gate includes at least one split region directly over the charge-trapping layer, and the charge-trapping layer around the split region serves as a coding region. A NAND non-volatile memory array is also described including the above-mentioned split-gate non-volatile memory cells that are arranged in a NAND-type configuration.

## Claims

### Claim 1

A split-gate non-volatile memory cell, comprising:
a substrate;
a charge-trapping layer on the substrate;
a split gate as a whole located over the charge-trapping layer, being a part of one word line of a non-volatile memory array including the split-gate non-volatile memory cell; and
a source/drain in the substrate beside the split gate,
wherein the split gate includes at least two neighboring conductive pieces that are shorted with each other and have two opposite edge portions together causing, in operation of the memory cell, a locally stronger electric field such that only one coding region is defined, by the two neighboring conductive pieces, in the charge-trapping layer around the two opposite edge portions.

### Claim 2 (depends on 1)

The split-gate non-volatile memory cell of claim 1, wherein the conductive pieces of the split gate include a pair of conductive spacers and a conductive layer between the pair of conductive spacers.

### Claim 3 (depends on 2)

The split-gate non-volatile memory cell of claim 2, wherein the pair of conductive spacers are arranged with two substantially vertical sidewalls thereof adjacent to the source/drain.

### Claim 4 (depends on 3)

The split-gate non-volatile memory cell of claim 3, further comprising an insulator on the source/drain, wherein the pair of conductive spacers are disposed on the sidewalls of the insulator.

### Claim 5 (depends on 1)

The split-gate non-volatile memory cell of claim 1, wherein the conductive pieces are separated from each other by a dielectric layer.

### Claim 6 (depends on 1)

The split-gate non-volatile memory cell of claim 1, wherein the split gate comprises polysilicon.

### Claim 7 (depends on 1)

The split-gate non-volatile memory cell of claim 1, wherein the charge-trapping layer comprises a silicon nitride layer disposed between two silicon oxide layers.

### Claim 8 (depends on 1)

The split-gate non-volatile memory cell of claim 1, wherein the charge-trapping layer comprises aluminum oxide (Al2O3).

### Claim 9 (depends on 1)

The split-gate non-volatile memory cell of claim 1, wherein the substrate comprises a p-substrate, and the source/drain comprises an n-type source/drain.

### Claim 10

An operating method of a split-gate non-volatile memory cell, wherein
the split-gate non-volatile memory cell comprises:
a substrate;
a charge-trapping layer on the substrate;
a split gate as a whole located over the charge-trapping layer, being a part of one word line of a non-volatile memory array including the split-gate non-volatile memory cell; and
a source/drain in the substrate beside the split gate,
wherein the split gate includes at least two neighboring conductive pieces that are shorted with each other and have two opposite edge portions together causing, in operation of the memory cell, a locally stronger electric field such that only one coding region is defined, by the two neighboring conductive pieces, in the charge-trapping layer around the two opposite edge portions;
and the operating method comprises:
in a programming operation:
applying 0V to the substrate and the source/drain; and
applying a first negative voltage to the split gate, the first negative voltage being sufficiently high for injecting electrons into the coding region; and
in an erasing operation:
applying 0V to the split gate, wherein each conductive piece is at an electric state of 0 V;
floating the source/drain; and
applying a second negative voltage to the substrate, the second negative voltage being sufficiently high for ejecting electrons from the coding region.

### Claim 11 (depends on 10)

The operating method of claim 10, wherein the first negative voltage is about −10V.

### Claim 12 (depends on 10)

The operating method of claim 10, wherein the second negative voltage is about −10V.