# US 7,608,880 B2 · Semiconductor memory device having a peripheral region including operating capacitors

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- Number: US 7,608,880 B2
- Document ID: US7608880B2
- Status: Granted
- Kind: B2
- Application number: 11/326,159
- Filed: 2006-01-05
- Published: 2006-07-20
- Granted: 2009-10-27
- Earliest claimed: 2005-01-18
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Bo-Tak Lim; Su-Yeon Kim; Jong-Pil Son; Gong-Heum Han
- Web page: https://patentgrep.com/patent/US7608880B2

## CPC

- H10D 89/10: Integrated device layouts
- H10B 12/50: {Peripheral circuit region structures}
- H10D 84/998: {Input and output buffer/driver structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a peripheral circuit region comprising a plurality of peripheral circuit devices including first transistors and second transistors and at least one operating capacitor formed adjacent to at least one peripheral circuit device; and
a cell region having the plurality of unit memory cells,
wherein a pattern density of the peripheral circuit region and a pattern density of the cell region are substantially the same without using a dummy pattern in the peripheral circuit region.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the at least one operating capacitor is formed at a pseudo circuit pattern region.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the at least one operating capacitor is a metal oxide semiconductor capacitor of which a gate electrode is a first pole plate, and a drain electrode and a source electrode are a second pole plate.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein the first transistors have a variety of gate electrode widths and the second transistors have a gate electrode width that is larger than any of the variety of gate electrode widths of the first transistors.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein a sum of a gate electrode width of the at least one operating capacitor disposed in a same column of the first transistor and a gate electrode width of the first transistor is less than a gate electrode width of a the second transistor.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the peripheral circuit devices are N-type MOS transistors or P-type MOS transistors.

### Claim 7 (depends on 4)

The semiconductor memory device of claim 4, wherein a gate electrode length of the at least one operating capacitor disposed opposite the first transistors successively formed in the same row is substantially equal to the sum of gate electrode lengths of the first transistors and distances between gate electrodes of the first transistors.