# US 7,608,879 B2 · Semiconductor device including a capacitance

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- Number: US 7,608,879 B2
- Document ID: US7608879B2
- Status: Granted
- Kind: B2
- Application number: 11/840,612
- Filed: 2007-08-17
- Published: 2007-12-27
- Granted: 2009-10-27
- Earliest claimed: 2001-09-19
- Assignees: Renesas Technology Corp.
- Inventors: Shigenobu Maeda; Takashi Ipposhi; Yuuichi Hirano
- Web page: https://patentgrep.com/patent/US7608879B2

## CPC

- H10D 86/01: Manufacture or treatment
- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/215: {of only varactors}
- H10D 84/217: {of only conductor-insulator-semiconductor capacitors}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

## Claims

### Claim 1

A semiconductor device comprising:
an insulated gate type capacitance formed in a semiconductor substrate,
said insulated gate type capacitance including,
a gate insulating film for said capacitance selectively formed on said semiconductor substrate,
a gate electrode for said capacitance formed on said gate insulating film for said capacitance and having opposed ends, and
extraction electrode regions formed to interpose therebetween a body region for said capacitance which is provided directly below said gate electrode for said capacitance in a surface of said semiconductor substrate, and
said gate electrode for said capacitance having first and second contact pad portions of the opposed ends of the gate electrode, wherein said first and second contact pad portions are electrically connected with a wiring.

### Claim 2

A semiconductor device comprising:
an insulated gate type capacitance formed in a semiconductor substrate,
said insulated gate type capacitance including,
a gate insulating film for said capacitance selectively formed on said semiconductor substrate,
a gate electrode for said capacitance formed on said gate insulating film for said capacitance and having opposite ends, and
extraction electrode regions formed to interpose therebetween a body region for said capacitance which is provided directly below said gate electrode for said capacitance in a surface of said semiconductor substrate, and
said gate electrode for said capacitance having first and second contact pad portions of the opposite ends of the gate electrode; and
first and second wiring formed along a virtual line, respectively, as seen on a plane,
said first and second contact pad portions are electrically connected with said first wiring, and
said second wiring electrically connected to said extraction electrode regions.