# US 7,608,878 B2 · Semiconductor device manufactured with a double shallow trench isolation process

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- Number: US 7,608,878 B2
- Document ID: US7608878B2
- Status: Granted
- Kind: B2
- Application number: 11/647,324
- Filed: 2006-12-29
- Published: 2008-01-03
- Granted: 2009-10-27
- Earliest claimed: 2006-06-30
- Assignees: Hynix Semiconductor Inc.
- Inventors: Seung Joo Baek
- Web page: https://patentgrep.com/patent/US7608878B2

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/0278: {forming single crystalline channels on wafers after forming insulating device isolations}
- H10D 64/027: {by etching at gate locations}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a semiconductor device includes forming a device isolation film by a double Shallow Trench Isolation (STI) process, forming a first active region having a negative slope and a second active region having a positive slope. Additionally, the method includes applying a recess region and a bulb-type recess region to the above-extended active region so as to prevent generation of horns in the active regions. This structure results in improvement in effective channel length and area.

## Claims

### Claim 1

A semiconductor device comprising:
a first trench formed in a semiconductor substrate, wherein sidewalls of the first trench have a negative slope;
a second trench formed in the semiconductor substrate below the first trench such that the second trench is in communication with the first trench, wherein sidewalls of the second trench have a positive slope;
a device isolation film for filling the first and second trenches;
an active region defined by the device isolation film; and
a gate formed over the active region, wherein the gate comprises a recess region,
wherein a depth of the first trench is substantially equal to or greater than a depth of the recess region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the first trench increases as the depth of the first trench increases.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a width of the second trench decreases as a depth of the second trench increases.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the recess region is disposed in the semiconductor substrate under the gate, a lower part of the recess region being ‘U’-shaped in a longitudinal direction of the active region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the gate further comprises a bulb-type region disposed under the recess region, wherein the bulb-type region is spherically shaped by isotropic-etching a lower part of the recess region.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the first recess region comprises the active region having a center defined by the second trench, the center being etched to a given depth, and
wherein the bulb-type region is ‘U’-shaped in a longitudinal direction of the active region.