# US 7,608,876 B2 · Merged MOS-bipolar capacitor memory cell

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- Number: US 7,608,876 B2
- Document ID: US7608876B2
- Status: Granted
- Kind: B2
- Application number: 11/452,025
- Filed: 2006-06-13
- Published: 2006-10-12
- Granted: 2009-10-27
- Earliest claimed: 2002-08-29
- Assignees: Micron Technology, Inc.
- Inventors: Leonard Forbes
- Web page: https://patentgrep.com/patent/US7608876B2

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10D 30/711: {having floating bodies}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10B 12/10: DRAM devices comprising bipolar components
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and a collector region. The base region for the vertical bi-polar transistor serves as the source region for the vertical MOS transistor. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical MOS transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor. The base region for the vertical bi-polar transistor is coupled to a write data word line.

## Claims

### Claim 1

A memory array, comprising:
a number of memory cells formed on a substrate, wherein each memory cell includes:
a semiconductor pillar, including:
a first conductivity region with n-type doping on a substrate;
a second conductivity region with p-type doping on the first conductivity region;
a third conductivity region with n-type doping on the second conductivity region; and
a fourth conductivity region with p-type doping on the third conductivity region;
a gate adjacent to and separated from the third conductivity region on a first side of the semiconductor pillar; and
a body capacitor, including the third conductivity region and a capacitor plate adjacent to and separated from the third conductivity region on a second side of the semiconductor pillar.

### Claim 2 (depends on 1)

The memory array of claim 1, wherein the first conductivity region is adapted to function as an emitter of a bi-polar transistor, the second conductivity region is adapted to function as a base region for a bi-polar transistor, and the third conductivity region is adapted to function as a collector region of a bi-polar transistor and as a body region of a MOS transistor.

### Claim 3 (depends on 2)

The memory array of claim 2, wherein the MOS transistor includes a p-channel MOS transistor (PMOS) and the bi-polar transistor includes an NPN bi-polar transistor.

### Claim 4 (depends on 1)

The memory array of claim 1, wherein the memory cell has an area of 4F2, where F is a minimum feature size.

### Claim 5 (depends on 1)

The memory array of claim 1, wherein the bi-polar transistor is operable to modulate the threshold voltage and conductivity of the MOS transistor in each memory cell.

### Claim 6 (depends on 1)

The memory array of claim 1, wherein the memory array is included in a dynamic random access memory (DRAM) chip.

### Claim 7

A memory array, comprising:
a number of memory cells formed on a substrate, wherein each memory cell includes:
a semiconductor pillar, including:
a first conductivity region with n-type doping on a substrate;
a second conductivity region with p-type doping on the first conductivity region;
a third conductivity region with n-type doping on the second conductivity region; and
a fourth conductivity region with p-type doping on the third conductivity region;
a gate adjacent to and separated from the third conductivity region on a first side of the semiconductor pillar; and
a body capacitor, including the third conductivity region and a capacitor plate adjacent to and separated from the third conductivity region on a second side of the semiconductor pillar; and
wherein the memory cell has an area of 4F2, where F is a minimum feature size.

### Claim 8 (depends on 7)

The memory array of claim 7, wherein the memory array is included in a dynamic random access memory (DRAM) chip.

### Claim 9 (depends on 7)

The memory array of claim 7, wherein the first conductivity region is adapted to function as an emitter of a bi-polar transistor.

### Claim 10 (depends on 7)

The memory array of claim 7, wherein the second conductivity region is adapted to function as a base region for a bi-polar transistor.

### Claim 11 (depends on 7)

The memory array of claim 7, wherein the third conductivity region is adapted to function as a collector region of a bi-polar transistor.

### Claim 12 (depends on 7)

The memory array of claim 7, wherein the third conductivity region is adapted to function as a body region of a MOS transistor.

### Claim 13 (depends on 12)

The memory array of claim 12, wherein the MOS transistor includes a p-channel MOS transistor (PMOS).

### Claim 14

A memory array, comprising:
a number of memory cells formed on a substrate, wherein each memory cell includes:
a semiconductor pillar, including:
a first conductivity region on a substrate;
a second conductivity region on the first conductivity region;
a third conductivity region on the second conductivity region; and
a fourth conductivity region on the third conductivity region;
a gate adjacent to and separated from the third conductivity region on a first side of the semiconductor pillar; and
a body capacitor, including the third conductivity region and a capacitor plate adjacent to and separated from the third conductivity region on a second side of the semiconductor pillar; and
wherein the first conductivity region is adapted to function as an emitter of a bi-polar transistor, the second conductivity region is adapted to function as a base region for a bi-polar transistor, and the third conductivity region is adapted to function as a collector region of a bi-polar transistor and as a body region of a MOS transistor.

### Claim 15 (depends on 14)

The memory array of claim 14, wherein the first conductivity region includes n-type doping.

### Claim 16 (depends on 14)

The memory array of claim 14, wherein the second conductivity region includes p-type doping.

### Claim 17 (depends on 14)

The memory array of claim 14, wherein the third conductivity region includes n-type doping.

### Claim 18 (depends on 14)

The memory array of claim 14, wherein the fourth conductivity region includes p-type doping.

### Claim 19 (depends on 14)

The memory array of claim 14, wherein the memory array is included in a dynamic random access memory (DRAM) chip.

### Claim 20 (depends on 14)

The memory array of claim 14, wherein each memory cell has an area of 4F2, where F is a minimum feature size.