# US 7,608,875 B2 · Method and apparatus for blocking light to peripheral circuitry of an imager device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,875 B2 - Document ID: US7608875B2 - Status: Granted - Kind: B2 - Application number: 11/289,553 - Filed: 2005-11-30 - Published: 2007-05-31 - Granted: 2009-10-27 - Earliest claimed: 2005-11-30 - Assignees: Aptina Imaging Corporation - Inventors: Zhaohui Yang; Ulrich C. Boettiger - Web page: https://patentgrep.com/patent/US7608875B2 ## CPC - H10F 39/024: {of coatings or optical elements} - H10F 39/8057: {Optical shielding} - H10F 39/8063: {Microlenses} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract Methods and apparatuses are disclosed which provide imager devices having a light blocking material layer formed over peripheral circuitry outside a pixel cell array. ## Claims ### Claim 1 An integrated circuit, comprising: a die; a pixel cell array formed in association with a semiconductor substrate incorporated on the die; a plurality of microlenses formed over a first material layer and the pixel cell array; peripheral circuitry formed in association with the die and electrically connected to the pixel cell array; a frame element forming a perimeter around the peripheral circuitry, the frame element having at least one recess defined by at least two portions of the frame element; and a substantially opaque material formed within the frame element recess and over the at least two portions to form an interface between the frame element and the substantially opaque material. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the frame element is formed over the first material layer. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the frame element is formed as at least two mesas of a second material formed over the semiconductor substrate included within the integrated circuit. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the first material layer is a planarization layer. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the frame element is formed as at least two mesa portions of the first material layer. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the substantially opaque material comprises a negative photoresist. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the frame element and the microlenses are comprised of a same material. ### Claim 8 (depends on 1) The integrated circuit of claim 1, wherein the frame element and the microlenses are formed on a same horizontal plane as the first material layer. ### Claim 9 (depends on 1) The integrated circuit of claim 1, wherein the pixel cell array further comprises a color filter array, and the frame element and color filter array are comprised of a same material. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the frame element and the color filter array are formed on a same horizontal plane as the first material layer. ### Claim 11 (depends on 1) The integrated circuit of claim 1, wherein the substantially opaque material has a sidewall surface substantially planar to a surface of one of the portions defining the recess. ### Claim 12 (depends on 1) The integrated circuit of claim 1, wherein the frame element is formed of a negative photoresist. ### Claim 13 (depends on 1) The integrated circuit of claim 1, wherein a thickness of the substantially opaque material within the recess is less than a thickness of the substantially opaque material over the at least two portions. ### Claim 14 An imager processor system, comprising: a processor; and an integrated circuit, comprising; a die; a pixel cell array formed in association with a semiconductor substrate incorporated on the die; circuitry formed in association with the die and electrically connected to the pixel cell array; a frame element formed by a first mesa and a second mesa, the first and second mesas defining at least one via having a bottom surface substantially planar to a bottom surface of at least one microlens of a plurality of microlenses formed over the pixel cell array, the first and second mesas forming a perimeter around the circuitry; and a substantially opaque material formed within the via and over portions of the first and second mesas to form an interface between the frame element and the substantially opaque material. ### Claim 15 (depends on 14) The processor system of claim 14, wherein the substantially opaque material and the plurality of microlenses are formed on a first material layer. ### Claim 16 (depends on 14) The processor system of claim 14, wherein the first mesa, the second mesa, and the plurality of microlenses are formed of a same material. ### Claim 17 (depends on 14) The processor system of claim 14, wherein the first and second mesas are formed as portions of a material layer extending through and above a planarization layer. ### Claim 18 (depends on 14) The processor system of claim 14, wherein the substantially opaque material comprises a negative photoresist. ### Claim 19 (depends on 14) The processor system of claim 14, wherein the first and second mesas are formed on a material layer on which the plurality of microlenses are formed. ### Claim 20 (depends on 14) The processor system of claim 14, wherein a thickness of the substantially opaque material within the via is less than a thickness of the substantially opaque material over the first and second mesas. ### Claim 21 An integrated circuit, comprising: a die having a pixel array and peripheral circuitry; a frame element forming a perimeter around the peripheral circuitry, the frame element having at least one recess defined by at least two portions of the frame element; and a substantially opaque material formed within the frame element recess and over the at least two portions to form an interface between the frame element and the substantially opaque material, the substantially opaque material being over the peripheral circuitry but not the pixel array. ### Claim 22 (depends on 21) The integrated circuit of claim 21, further comprising a plurality of microlenses formed over a first material and the pixel cell array, wherein the frame element is formed over the first material. ### Claim 23 (depends on 21) The integrated circuit of claim 21, wherein the frame element is formed as at least two mesas of a second material formed over the semiconductor substrate included within the integrated circuit. ### Claim 24 (depends on 21) The integrated circuit of claim 21, wherein the first material is a planarization layer. ### Claim 25 (depends on 21) The integrated circuit of claim 21, wherein the frame element is formed as at least two mesa portions of the first material. ### Claim 26 (depends on 21) The integrated circuit of claim 21, wherein the frame element and the microlenses are comprised of a same material. ### Claim 27 (depends on 21) The integrated circuit of claim 21, wherein the pixel cell array further comprises a color filter array, and the frame element and color filter array are comprised of a same material. ### Claim 28 (depends on 21) The integrated circuit of claim 21, wherein a thickness of the substantially opaque material within the recess is less than a thickness of the substantially opaque material over the at least two portions.