# US 7,608,874 B2 · Fully isolated photodiode stack

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,608,874 B2
- Document ID: US7608874B2
- Status: Granted
- Kind: B2
- Application number: 11/657,152
- Filed: 2007-01-24
- Published: 2007-09-20
- Granted: 2009-10-27
- Earliest claimed: 2006-03-17
- Assignees: Sharp Laboratories of America, Inc.
- Inventors: Jong-Jan Lee; Douglas J. Tweet; Sheng Teng Hsu
- Web page: https://patentgrep.com/patent/US7608874B2

## CPC

- H10F 39/1825: {Multicolour image sensors having stacked structure, e.g. NPN, NPNPN or multiple quantum well [MQW] structures}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/807: {Pixel isolation structures}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.

## Claims

### Claim 1

An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells, the color imager cell array comprising:
a bulk silicon (Si) substrate;
a single layer of epitaxial Si overlying the substrate, including a plurality of color imager cells, where each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure; and,
a U-shaped well liner, fully isolating each photodiode set from adjacent photodiode sets in the array.

### Claim 2 (depends on 1)

The color imager cell array of claim 1 wherein each photodiode includes a doped Si layer physically interfacing the well liner.

### Claim 3 (depends on 2)

The color imager cell array of claim 2 wherein the well liner includes a first wall physically interfacing a doped Si layer of each photodiode in the photodiode set.

### Claim 4 (depends on 3)

The color imager cell array of claim 3 wherein each photodiode includes a p doped Si layer physically interfacing the first wall; and,
wherein the well liner is p doped and electrically connected to a reference voltage.

### Claim 5 (depends on 4)

The color imager cell array of claim 4 wherein the well liner includes a well bottom physically interfacing the first wall; and,
wherein the third, bottom-most, photodiode includes a p doped layer that is part of the well bottom.

### Claim 6 (depends on 5)

The color imager cell array of claim 5 wherein the first photodiode includes a first doped Si layer formed in a top surface region, and an underlying first p doped Si layer physically interfacing the first wall;
wherein the second photodiode includes a second doped Si layer underlying the first p doped Si layer, an underlying second p doped Si layer physically interfacing the first wall, and an n doped first vertical structure physically interfacing the second doped Si layer to a top surface region; and,
wherein the third photodiode includes a third doped Si layer underlying the second p doped Si layer, an underlying third p doped Si layer physically interfacing the first wall and forming a portion of the well bottom, and an n doped second vertical structure physically interfacing the third doped Si layer to a top surface region.

### Claim 7 (depends on 6)

The color imager cell array of claim 6 wherein the well liner includes a p doped second wall physically interfacing the second vertical structure, the third doped Si layer, and the well bottom.

### Claim 8 (depends on 7)

The color imager cell array of claim 7 wherein the first, second, and third doped Si layers are n doped.

### Claim 9 (depends on 6)

The color imager cell array of claim 6 wherein the first doped Si layer is n doped, and the second and third Si layers are p doped.

### Claim 10 (depends on 6)

The color imager cell array of claim 6 further comprising:
isolating structures separating the first and second vertical structures, and separating the first vertical structure and the first doped Si layer, the isolating structures selected from a group consisting of dielectric material, p doped Si, and combinations of dielectric material and p doped Si.

### Claim 11 (depends on 1)

The color imager cell array of claim 1 wherein the photodiode set multi-junction structure is formed in the Si substrate.

### Claim 12

A method for forming an array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells, the method comprising:
providing a bulk silicon (Si) substrate;
forming a layer of epitaxial Si overlying the substrate;
forming a plurality of color imager cells, where each color imager cell includes a photodiode set formed in the epitaxial Si layer, with a first, second, and third photodiode formed as a stacked multi-junction structure; and,
forming a U-shaped well liner, fully isolating each photodiode set from adjacent photodiode sets in the array.

### Claim 13 (depends on 12)

The method of claim 12 wherein forming the photodiode set includes forming each photodiode with a doped Si layer physically interfaced to the well liner.

### Claim 14 (depends on 13)

The method of claim 13 wherein forming the well liner includes forming a well liner first wall physically interfaced to a doped Si layer of each photodiode.

### Claim 15 (depends on 14)

The method of claim 14 wherein forming the photodiodes includes forming each photodiode with a p doped Si layer physically interfaced to the well liner; and,
wherein forming the well liner includes forming a p doped well liner electrically connected to a reference voltage.

### Claim 16 (depends on 15)

The method of claim 15 wherein forming the well liner includes forming a well bottom physically interfaced to the first wall; and,
wherein forming the photodiodes includes forming the third, bottom-most, photodiode with a p doped layer that is part of the well bottom.

### Claim 17 (depends on 16)

The method of claim 16 wherein forming the first photodiode includes forming the first photodiode with a first doped Si layer formed in a top surface region, and an underlying first p doped Si layer physically interfaced to the first wall;
wherein forming the second photodiode includes forming the second photodiode with a second doped Si layer underlying the first p doped Si layer, an underlying second p doped Si layer physically interfaced to the first wall, and an n doped first vertical structure physically interfacing the second doped Si layer to a top surface region; and,
wherein forming the third photodiode includes forming a third doped Si layer underlying the second p doped Si layer, an underlying third p doped Si layer physically interfaced to the first wall and forming a portion of the well bottom, and an n doped second vertical structure physically interfacing the third doped Si layer to a top surface region.

### Claim 18 (depends on 17)

The method of claim 17 wherein forming the well liner includes forming a p doped second wall physically interfaced to the second vertical structure, the third doped Si layer, and the well bottom.

### Claim 19 (depends on 17)

The method of claim 17 wherein forming the photodiode set includes forming first, second, and third n doped Si layers.

### Claim 20 (depends on 17)

The method of claim 17 wherein forming the photodiode set includes forming a first n doped Si layer, and second and third p doped Si layers.

### Claim 21 (depends on 17)

The method of claim 17 wherein forming the well liner includes:
prior to forming the photodiode set doped Si layers, p doping a horizontal layer of the Si substrate, forming the well bottom; and
p doping vertical sections, forming the well liner first and second walls.

### Claim 22 (depends on 21)

The method of claim 21 wherein forming the well bottom includes:
doping with a boron concentration in a range of 5×1016 to 1×1019 per cubic centimeter (cm−3);
forming a well bottom layer with a thickness in a range of about 0.5 to 2 microns; and,
forming the well bottom a depth in a range of about 2 to 6 microns below the top surface.

### Claim 23 (depends on 21)

The method of claim 21 wherein forming the well liner first and second wall includes:
doping with a boron concentration in a range of 5×1016 to 1×1019 cm−3; and,
forming vertical structures extending a depth in a range of about 2 to 6 microns below the top surface.

### Claim 24 (depends on 12)

The method of claim 12 wherein forming the photodiode set includes forming the photodiode set in the Si substrate.