# US 7,608,851 B2 · Switch array circuit and system using programmable via structures with phase change materials

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- Number: US 7,608,851 B2
- Document ID: US7608851B2
- Status: Granted
- Kind: B2
- Application number: 11/745,811
- Filed: 2007-05-08
- Published: 2008-11-13
- Granted: 2009-10-27
- Earliest claimed: 2007-05-08
- Assignees: International Business Machines Corporation
- Inventors: Kuan-Neng Chen; Chung H. Lam
- Web page: https://patentgrep.com/patent/US7608851B2

## CPC

- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H03K 19/1736: {in which the wiring can be modified}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/253: {having three or more electrodes, e.g. transistor-like devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8613: {Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10N 79/00: Integrated devices, or assemblies of multiple devices, comprising at least one solid-state element covered by group H10N70/00 (ReRAM devices H10B63/00; PCRAM devices H10B63/10)
- H10B: ELECTRONIC MEMORY DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A programmable via structure that includes at least two phase change material vias each directly contacting a heating element, the via structure further including a first terminal in contact with a first heating element portion, a second terminal in contact with a second heating element portion, a third terminal in contact with one of the vias, and a fourth terminal in contact with another one of the vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first transistor in contact with one of the first and second terminals; and a drain region of a second transistor in contact with the first or second terminal that is not contacting the source region of the first transistor.

## Claims

### Claim 1

A switch unit comprising:
a programmable via structure including at least a first phase change material via directly contacting a bottom surface of a heating element and a second phase change material via directly contacting an upper surface of said heating element, said programmable via structure further including a first terminal in contact with a first portion of said heating element, a second terminal in contact with a second portion of said heating element, a third terminal in contact with said first phase change material via, and a fourth terminal in contact with said second phase change material via;
a first circuit block in contact with one of said third and fourth terminals;
a second circuit block in contact with the third or fourth terminal not contacting said first circuit block;
a source region of a first field effect transistor in contact with one of said first and second terminals; and
a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting said source region of said first field effect transistor.

### Claim 2 (depends on 1)

The switch unit of claim 1 further comprising a first dielectric layer located on a surface of a semiconductor substrate, said first dielectric layer having a conductive material embedded therein; a second dielectric layer located atop the first dielectric layer and said conductive material, said second dielectric layer including said first phase change material via, said first phase change material via having a surface directly contacting an upper surface of the conductive material, said heating element is located on an upper surface of the second dielectric layer and directly atop said first phase change material via; a third dielectric layer having the second phase change material via located on said heating element and exposed surfaces of said second dielectric layer; and a patterned diffusion barrier located on an exposed surface of said second phase change material via.

### Claim 3 (depends on 1)

The switch unit of claim 1 wherein each of said phase change material vias includes a chalcogenide material or a chalcogenide alloy.

### Claim 4 (depends on 3)

The switch unit of claim 3 wherein said chalcogenide material or chalcogenide alloy is one of Ge2Sb2Te5 and GeSb.

### Claim 5 (depends on 1)

The switch unit of claim 1 wherein said heating element is a nitride or an oxide having a resistivity of about 100 ohm cm or greater.

### Claim 6 (depends on 5)

The switch unit of claim 5 wherein said heating element is TaxSiyNz where x, y and z are approximately from 0 to 1, CrO2 or RuO2.

### Claim 7 (depends on 1)

The switch unit of claim 1 wherein said first field effect transistor further includes a drain region in contact with a bit line, and a gate of said first field effect transistor is in contact with a write line.

### Claim 8 (depends on 1)

The switch unit of claim 1 wherein said second field effect transistor further includes a source region in contact to ground, and a gate of said second field effect transistor is in contact with a write line.

### Claim 9 (depends on 1)

The single switch unit of claim 1 wherein said first field effect transistor further includes a drain region in contact with a bit line, and a gate of said first field effect transistor is in contact a write line, and said second field effect transistor further includes a source region in contact to ground, and a gate of said second field effect transistor is in contact with said write line.

### Claim 10

A switch unit array comprising:
a plurality of programmable via structures, each programmable via structure including a first phase change material via directly contacting a bottom surface of a heating element and a second phase change material via directly contacting an upper surface of said heating element, said programmable via structure further including a first terminal in contact with a first portion of said heating element, a second terminal in contact with a second portion of said heating element, a third terminal in contact with said first phase change material via, and a fourth terminal in contact with said second phase change material via; a first circuit block in contact with one of said third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting said first circuit block; a source region of a first field effect transistor in contact with one of said first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting said source region of said first field effect transistor.

### Claim 11 (depends on 10)

The switch unit array of claim 10 wherein each programmable via structure further comprising a first dielectric layer located on a surface of a semiconductor substrate, said first dielectric layer having a conductive material embedded therein; a second dielectric layer located atop the first dielectric layer and said conductive material, said second dielectric layer including said first phase change material via, said first phase change material via having a surface directly contacting an upper surface of the conductive material, said heating element is located on an upper surface of the second dielectric layer and directly atop said second phase change material via; a third dielectric layer having the second phase change material via located on said heating element and exposed surfaces of said second dielectric layer; and a patterned diffusion barrier located on an exposed surface of said second phase change material via.

### Claim 12 (depends on 10)

The switch unit array of claim 10 wherein each of said phase change material vias includes a chalcogenide material or a chalcogenide alloy.

### Claim 13 (depends on 10)

The switch unit array of claim 10 wherein each heating element is a nitride or an oxide having a resistivity of about 100 ohm cm or greater.

### Claim 14 (depends on 13)

The switch unit array of claim 13 wherein each heating element is TaxSiyNz where x, y and z are approximately from 0 to 1, CrO2 or RuO2.

### Claim 15 (depends on 10)

The switch unit array of claim 10 wherein each of said first field effect transistors further includes a drain region in contact with a bit line, and a gate of each of said first field effect transistor is in contact with a write line.

### Claim 16 (depends on 10)

The switch unit array of claim 10 wherein each of said second field effect transistors further includes a source region in contact to ground, and a gate of each of said second field effect transistors is in contact with a write line.

### Claim 17 (depends on 10)

The single switch unit array of claim 10 wherein each of said first field effect transistors further includes a drain region in contact with a bit line, and each gate of said first field effect transistors is in contact with a write line, and each second field effect transistor further includes a source region in contact to ground, and each gate of said second field effect transistor is in contact with said write line.