# US 7,608,536 B2 · Method of manufacturing contact opening

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,608,536 B2
- Document ID: US7608536B2
- Status: Granted
- Kind: B2
- Application number: 11/984,054
- Filed: 2007-11-13
- Published: 2009-01-01
- Granted: 2009-10-27
- Earliest claimed: 2007-06-29
- Assignees: Hynix Semiconductor Inc.
- Inventors: Jung Seock Lee; Hyun Suk Sung
- Web page: https://patentgrep.com/patent/US7608536B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/097: {by thermally treating}
- H10W 20/076: {in via holes or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In this way, it is possible to prevent the storage node contact hole from not being opened.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a first interlayer insulating film over a semiconductor substrate having landing plug contacts provided therein;
forming a bit line pattern over the first interlayer insulating film;
recessing a portion of the first interlayer insulating film using the bit line pattern as a mask;
depositing a lining insulating film over the entire surface including the surface of the bit line pattern;
forming a second interlayer insulating film over the lining insulating film;
performing a CMP process until the bit line pattern is exposed; and
selectively etching the second interlayer insulating film and the first interlayer insulating film over the landing plug contact to form a storage node contact hole exposing the landing plug contact.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first interlayer insulating film is formed of an oxide film.

### Claim 3 (depends on 1)

The method of claim 1, wherein the bit line pattern comprises a stack structure of a bit line electrode layer of tungsten and a bit line hard mask layer of a nitride film.

### Claim 4 (depends on 1)

The method of claim 1, wherein the recessing of the first interlayer insulating film is performed using a dry etching method employing a carbon fluoride.

### Claim 5 (depends on 4)

The method of claim 4, wherein the carbon fluoride is any one of C4F8, C5F8, C3F8, and a combination thereof.

### Claim 6 (depends on 1)

The method of claim 1, wherein the recessed first interlayer insulating film has a thickness of 50 to 100 Å.

### Claim 7 (depends on 1)

The method of claim 1, wherein the lining insulating film includes a nitride film.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second interlayer insulating film is a SOD (spin on dielectric) oxide film.

### Claim 9 (depends on 1)

The method of claim 1, further comprising: performing an annealing process after the second interlayer insulating film is formed.

### Claim 10 (depends on 9)

The method of claim 9, wherein the annealing process is performed at a temperature of about 500 to about 700° C.

### Claim 11 (depends on 9)

The method of claim 9, wherein the annealing process is a wet annealing process using a gas comprising O2 and H2 gas or a dry annealing process using a gas comprising O2 gas.

### Claim 12 (depends on 1)

The method of claim 1, further comprising, after the forming of the storage node contact hole:
forming a spacer for a storage node over the inner wall of the storage node contact hole.