# US 7,608,513 B2 · Dual gate LDMOS device fabrication methods

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- Number: US 7,608,513 B2
- Document ID: US7608513B2
- Status: Granted
- Kind: B2
- Application number: 11/626,928
- Filed: 2007-01-25
- Published: 2008-07-31
- Granted: 2009-10-27
- Earliest claimed: 2007-01-25
- Assignees: Freescale Semiconductor, Inc.
- Inventors: Hongning Yang; Veronique C. Macary; Won Gi Min; Jiang-Kai Zuo
- Web page: https://patentgrep.com/patent/US7608513B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/0217: {forming self-aligned punch-through stoppers or threshold implants under gate regions}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 64/111: {Field plates}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising the steps of:
providing a semiconductor having a substrate region of a first conductivity type and first impurity concentration, extending to a surface of the semiconductor;
impurity doping a first region of the first conductivity type and a second dopant concentration in a first portion of the substrate region to form a first doped well extending substantially to the surface;
impurity doping a second region of a second, opposite conductivity type and a third dopant concentration within a second portion of the substrate region different from the first portion of the substrate region, thereby forming a second doped well extending substantially to the surface;
forming a first gate dielectric surmounted by a first gate, at least partially overlying the first region or the substrate region or both;
forming a second gate dielectric surmounted by a second gate, substantially overlying the second region and spaced apart from the first gate;
impurity doping a third region of the second conductivity type and a fourth impurity concentration in the substrate region, adapted when biased to form a depletion region at least partly in the substrate region or in a combination of the substrate region and the first region;
forming a bias contact to a part of the depletion region; and
electrically coupling the bias contact to the second gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of impurity doping a third region, comprises, forming as the third region, a lateral isolation wall of the second conductivity type at least partly encompassing the substrate region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the step of impurity doping a third region, comprises, forming as the third region, a drain region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the depletion region has a width when biased and the bias contact is located at a distance from the third region of about 50-75% of the width of the depletion region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the fourth dopant concentration is at least ten times the first dopant concentration.

### Claim 6 (depends on 1)

The method of claim 1, wherein the step of forming a bias contact, comprises, locating the bias contact within the depletion region so that when the depletion region is formed by biasing the third region, the voltage at the bias contact is in the range of about 50-75% of the maximum operating voltage of the device.

### Claim 7 (depends on 1)

The method of claim 1 wherein:
the step of impurity doping the second region, comprises, forming the second region spaced apart from the first region by a portion of the substrate region so that a PN junction formed between the second region and the substrate region extends substantially to the surface; and
the step of forming a first gate comprises forming the first gate substantially overlying a part of the substrate region.

### Claim 8 (depends on 1)

The method of claim 1 wherein:
the step of impurity doping a second region comprises, forming the second region substantially in contact with the first region so that a PN junction therebetween extends substantially to the surface; and
the step of forming a first gate comprises, forming the first gate mostly overlying the first region.

### Claim 9 (depends on 7)

The method of claim 7, wherein the bias contact is located within the depletion region, so that an electric field at a surface of the portion of the substrate region is reduced.

### Claim 10

A method of fabricating a semiconductor device, comprising the steps of:
providing a semiconductor substrate of a first conductivity type and first dopant concentration and having a surface;
forming a first well of the first conductivity type and second dopant concentration in the substrate;
forming a second well of a second, opposite, conductivity type and third dopant concentration in the substrate, wherein the second well is separated from or in contact with the first well and forms a PN junction with the first well or the substrate, which PN junction extends substantially to the surface;
forming a third region of the second conductivity type and a fourth dopant concentration in the substrate, extending substantially to the surface and laterally separated from the first well, and adapted when biased to form a space charge region at least partly in the substrate or the first well or in a combination thereof;
forming a first gate overlying a part of the first well or a part of the substrate between the first and second wells or both;
forming a second gate spaced apart from the first gate and overlying at least a part of the second well; and
forming an ohmic contact to the substrate within the space charge region and electrically coupled to the second gate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the ohmic contact to the substrate within the space-charge region is separated from the third region by a distance such that the ohmic contact sees a voltage when the third region is biased of about 50-75% of the maximum rated operating voltage of the device.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
forming a source of the second conductivity type in the first well; and
forming a drain region of the second conductivity type in the second well.

### Claim 13 (depends on 10)

The method of claim 10, wherein the third region is a lateral isolation wall.

### Claim 14 (depends on 10)

The method of claim 10, wherein a silicide blocking layer overlies the surface between the first and second gates and a voltage applied to the second gate by the ohmic contact to the substrate reduces, during operation, a maximum electric field at the surface underlying the silicide blocking layer compared to the maximum electric field underlying the silicide blocking layer when no second gate is present.

### Claim 15 (depends on 14)

The method of claim 14, wherein one lateral edge of the second gate and one lateral edge of the drain are substantially aligned, and one lateral edge of the first gate and one lateral edge of the source are substantially aligned.

### Claim 16 (depends on 10)

The method of claim 10, wherein the fourth dopant concentration is at least ten times larger than the first dopant concentration.

### Claim 17

A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) device, comprising the steps of:
providing a semiconductor substrate of a first conductivity type and first concentration, having a principal surface;
forming a source region of a second, opposite, conductivity type extending to the principal surface;
forming a drain region of a second, opposite, conductivity type extending to the principal surface and spaced apart from the source region;
forming a first gate above a first portion of the principal surface proximate the source region, wherein the first gate is adapted to receive a control signal;
forming a second gate above the principal surface proximate the drain region and spaced apart from the first gate, wherein the second gate is adapted to receive a bias voltage Vg2;
forming a further region in the substrate, wherein the further region is of the second conductivity type and further dopant concentration greater than the first concentration, and is adapted to form a space charge region in the substrate when the further region receives a voltage Vbias; and
forming a body contact within the space charge region and spaced a predetermined distance from the further region, wherein the body contact is coupled to the second gate for providing voltage Vg2 to the second gate, and wherein the space charge region acts as a voltage divider so that Vg2 provided by the body contact is a predetermined fraction of Vbias applied to the further region.

### Claim 18 (depends on 17)

The method of claim 17, wherein the predetermined fraction is in a range of 50 percent to 75 percent of Vbias.

### Claim 19 (depends on 18)

The method of claim 18, wherein the predetermined fraction is in a range of about 55 percent to about 65 percent of Vbias.

### Claim 20 (depends on 17)

The method of claim 17, wherein the further region is part of a lateral isolation wall, and the further dopant concentration is greater than 10 times the first dopant concentration.