# US 7,608,509 B2 · Method of manufacturing a flash memory device having compensation members formed on edge portions of a tunnel oxide layer

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- Number: US 7,608,509 B2
- Document ID: US7608509B2
- Status: Granted
- Kind: B2
- Application number: 11/494,439
- Filed: 2006-07-27
- Published: 2007-02-01
- Granted: 2009-10-27
- Earliest claimed: 2005-08-01
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Chul-Sung Kim; Yu-Gyun Shin; Bon-Young Koo; Sung-Kweon Baek; Young-Jin Noh
- Web page: https://patentgrep.com/patent/US7608509B2

## CPC

- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/6894: {having one gate at least partly in a trench}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device. Thus, the semiconductor device may have improved electrical characteristics and reliability.

## Claims

### Claim 1

A method of manufacturing a semiconductor device comprising:
forming preliminary isolation regions on a substrate to define an active region, the preliminary isolation regions having protruded upper portions;
forming an insulation layer on a portion of the active region exposed between the preliminary isolation regions;
forming a first conductive layer on the insulation layer to fill a space between the protruded upper portions of the preliminary isolation regions;
removing the protruded upper portions of the preliminary isolation regions to expose sidewalls of the first conductive layer; and
forming compensation members on edge portions of the insulation layer to have a thickness sufficient for preventing concentration of a Fowler-Nordheim tunneling through the edge portions of the insulation layer by oxidizing exposed lower edge portions of the first conductive layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the preliminary isolation regions comprises:
successively forming a pad oxide layer and a mask layer on the substrate;
partially etching the mask layer and the pad oxide layer to form a pad oxide layer pattern and a mask pattern on the substrate and to expose portions of the substrate;
partially etching the exposed portions of the substrate to form trenches on the substrate;
filling a preliminary isolation layer into the trenches to form the preliminary isolation regions; and
removing the mask pattern and the pad oxide layer pattern to form an opening exposing the active region between the preliminary isolation regions.

### Claim 3 (depends on 2)

The method of claim 2, further comprising enlarging the opening so that the opening has a width substantially greater than that of the active region.

### Claim 4 (depends on 3)

The method of claim 3, wherein the insulation layer formed on a bottom of the opening has a width substantially greater than that of the active region.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first conductive layer has a width substantially greater than that of the active region.

### Claim 6 (depends on 1)

The method of claim 1, wherein the compensation members are formed by a dry oxidation process or a wet oxidation process.

### Claim 7 (depends on 6)

The method of claim 6, wherein the compensation members are formed by a thermal oxidation process, a radical oxidation process, or a plasma oxidation process.

### Claim 8 (depends on 7)

The method of claim 7, wherein the thermal oxidation process and the radical oxidation process are performed at a temperature of about 800° C. to about 1100° C.

### Claim 9 (depends on 7)

The method of claim 7, wherein the plasma oxidation process is performed at a temperature of about 350° C. to about 800° C.

### Claim 10 (depends on 1)

The method of claim 1, wherein a first oxide film is formed on the first conductive layer while the compensation members are formed at the lower edge portions of the first conductive layer.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
forming a dielectric layer on the first conductive layer; and
forming a second conductive layer on the dielectric layer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
forming a nitride film on the first oxide film; and
forming a second oxide film on the nitride film.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
removing the first oxide film;
forming a dielectric layer on the first conductive layer; and
forming a second conductive layer on the dielectric layer.

### Claim 14 (depends on 1)

The method of claim 1, wherein the protruded upper portions of the preliminary isolation regions are removed until all of the sidewalls and lower edge portions of the first conductive layer are exposed.