# US 7,608,507 B2 · NAND flash memory devices and methods of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,507 B2 - Document ID: US7608507B2 - Status: Granted - Kind: B2 - Application number: 12/216,393 - Filed: 2008-07-03 - Published: 2008-10-30 - Granted: 2009-10-27 - Earliest claimed: 2005-08-26 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Ji-Hwon Lee; Sung-Hoi Hur - Web page: https://patentgrep.com/patent/US7608507B2 ## CPC - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - H10B 41/10: characterised by the top-view layout - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/10: characterised by the top-view layout - H10B 43/30: characterised by the memory core region - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors. ## Claims ### Claim 1 A method of fabricating a NAND flash memory device, comprising: defining a plurality of active regions in a substrate; forming memory transistors on the active regions, the memory transistors including memory gate patterns arranged perpendicular to the plurality of active regions; forming lower plugs electrically connected to first regions of the plurality of active regions; and forming select transistors above the memory gate patterns, the select transistors including impurity regions, at least one impurity region of each select transistor being electrically connected to a respective first region via a lower plug. ### Claim 2 (depends on 1) The method of claim 1, wherein defining the active regions further includes, forming device isolation patterns to define the plurality of active regions. ### Claim 3 (depends on 2) The method of claim 2, wherein dummy gate patterns are formed on device isolation patterns between two adjacent cell strings concurrently with the forming of the memory gate patterns, each dummy gate pattern being disposed parallel to the memory gate patterns. ### Claim 4 (depends on 1) The method of claim 1, wherein the forming of the memory transistors includes, forming a gate insulation layer on each active region, forming the plurality of memory gate patterns parallel to each other on the gate insulation layer, and performing an ion implantation process using the memory gate patterns as an ion mask to form lower impurity regions within the active regions on each side of the memory gate patterns. ### Claim 5 (depends on 1) The method of claim 1, wherein the forming of the lower plugs includes, forming a lower interlayer insulation layer on a resultant structure including the memory transistors, patterning the lower interlayer insulation layer to form contact holes exposing a portion of the lower impurity regions, and forming an epitaxial layer to form the lower plugs in the contact holes. ### Claim 6 (depends on 5) The method of claim 5, wherein the forming of the epitaxial layer includes, injecting impurities the same conductive type as the lower impurity regions in the epitaxial layer. ### Claim 7 (depends on 5) The method of claim 5, wherein the epitaxial layer is formed using a selective epitaxial process that grows the epitaxial layer locally from the active regions exposed through the contact holes. ### Claim 8 (depends on 1) The method of claim 1, wherein the lower plugs are formed on each sides of a cell string having a plurality of memory transistors to be connected to upper surfaces of the active regions, wherein one cell string includes 8 to 128 memory transistors connected in serial on one active region. ### Claim 9 (depends on 8) The method of claim 8, wherein device isolation patterns define the plurality of active regions, and the device isolation patterns are formed between two adjacent cell strings along the direction of the memory gate pattern. ### Claim 10 (depends on 8) The method of claim 8, wherein after forming the select transistors, the method further includes, forming a common source line connecting the upper impurity regions in a direction parallel to a direction of the memory gate patterns, and forming bit lines connecting the upper impurity regions in a direction perpendicular to the direction of the memory gate patterns, wherein the common source line and the bit lines are connected to different select transistors. ### Claim 11 (depends on 10) The method of claim 10, wherein the select transistor connected to the common source line is connected to an active region formed on one side of a cell string through the lower plug, and the select transistor connected to the bit line is connected to an active region formed on another side of the cell string through the lower plug. ### Claim 12 (depends on 1) The method of claim 1, wherein a dummy gate pattern is formed perpendicular to the active regions between two adjacent cell strings concurrently with the forming of the memory gate patterns. ### Claim 13 (depends on 1) The method of claim 1, wherein the forming of the select transistors includes, forming an upper active layer on a resultant structure including the lower plugs, the upper active layer having a conductive type identical to that of the substrate, forming upper active patterns connected to the lower plugs by patterning the upper active layer, forming a select gate insulation layer on each upper active pattern; forming a select gate pattern on each select gate insulation layer, the select gate patterns being disposed parallel to the memory gate patterns, and forming upper impurity regions at each side of each select gate pattern using the select gate patterns as an ion mask. ### Claim 14 (depends on 13) The method of claim 13, wherein the forming of the lower plugs includes, forming a lower interlayer insulation layer on a resultant structure including the memory transistors, forming contact holes exposing a portion of the lower impurity regions by patterning the lower interlayer insulation layer, and forming the lower plugs filling the contact holes using epitaxial growth. ### Claim 15 (depends on 13) The method of claim 13, wherein the forming of the upper active layer includes, forming an epitaxial layer covering the lower interlayer insulation layer, and forming the upper active patterns connected to the lower plugs by patterning the epitaxial layer, wherein the lower plug is formed of silicon having a conductive type different from that of the substrate, and the epitaxial layer is formed of silicon having a conductive type identical to that of the substrate. ### Claim 16 (depends on 15) The method of claim 15, wherein the epitaxial layer is formed using epitaxial growth. ### Claim 17 (depends on 13) The method of claim 13, wherein the forming of the upper active layer includes, forming an epitaxial layer covering the lower interlayer insulation layer, and forming the upper active patterns connected to the lower plugs by patterning the epitaxial layer, wherein the forming of the epitaxial layer includes, forming a lower silicon layer having a conductive type different from that of the substrate, and forming an upper silicon layer on the lower silicon layer, the upper silicon layer having a conductive type identical to that of the substrate. ### Claim 18 (depends on 13) The method of claim 13, wherein the forming of the upper active layer includes, depositing a polysilicon layer on a resultant structure including the lower plugs, the polysilicon layer having a conductive type identical to that of the substrate.