# US 7,608,505 B2 · Method of manufacturing non-volatile memory device

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- Number: US 7,608,505 B2
- Document ID: US7608505B2
- Status: Granted
- Kind: B2
- Application number: 11/643,880
- Filed: 2006-12-22
- Published: 2007-06-28
- Granted: 2009-10-27
- Earliest claimed: 2005-12-28
- Assignees: Dongbu Electronics Co., Ltd.
- Inventors: Yong Jun Lee
- Web page: https://patentgrep.com/patent/US7608505B2

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a non-volatile memory device includes the steps of: defining an active region on a semiconductor substrate; forming a charge storage layer on the active region; forming a first conductive pattern on the charge storage layer, wherein the first conductive pattern has a bottom portion larger in width than a top portion thereof, the first conductive pattern further having a sloping sidewall connecting the top and bottom portions; forming an oxide layer on the sidewall of the first conductive pattern; forming a conformal second conductive layer on the first conductive pattern and on the active region around the first conductive pattern; and patterning the first conductive pattern and the second conductive layer to form a pair of first electrodes and a pair of second electrodes, respectively.

## Claims

### Claim 1

A method of manufacturing a non-volatile memory device, the method comprising the steps of:
defining an active region on a semiconductor substrate;
forming a charge storage layer on the active region;
forming a first conductive pattern on the charge storage layer, wherein the first conductive pattern has a bottom portion larger in width than a top portion thereof, the first conductive pattern further having a sloping sidewall connecting the top and bottom portions;
forming an oxide layer on the sloping sidewall of the first conductive pattern;
forming a conformal second conductive layer on the first conductive pattern and on the active region around the first conductive pattern; and
patterning the first conductive pattern and the second conductive layer to form a pair of first electrodes and a pair of second electrodes, respectively.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of forming the first conductive pattern includes:
forming a first conductive layer on the charge storage layer; and
pattering the first conductive layer to form the first conductive pattern.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a capping insulating layer on a top of the first conductive layer;
wherein the capping insulating layer and the first conductive layer are simultaneously patterned in the step of pattering the first conductive layer to form the first conductive pattern.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of forming the oxide layer is performed by using a high temperature oxidation process.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
annealing the oxide layer formed by the high temperature oxidation process.

### Claim 6 (depends on 1)

The method of claim 1, further comprising the steps of:
removing a portion of the charge storage layer on which the first conductive pattern is not formed; and
forming a gate insulating layer on the active region where the portion of the charge storage layer has been removed.

### Claim 7 (depends on 2)

The method of claim 2, wherein the step of forming the oxide layer is performed by using a high temperature oxidation process.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
annealing the oxide layer formed by the high temperature oxidation process.

### Claim 9 (depends on 2)

The method of claim 2, further comprising the steps of:
removing a portion of the charge storage layer on which the first conductive pattern is not formed; and
forming a gate insulating layer on the active region where the portion of the charge storage layer has been removed.

### Claim 10 (depends on 2)

The method of claim 2, wherein the step of pattering the first conductive layer to form the first conductive pattern includes:
etching the first conductive layer while controlling a process parameter to whereby form the sloping sidewall of the first conductive pattern.

### Claim 11 (depends on 10)

The method of claim 10, wherein the process parameter being controlled is a reaction gas used during said etching.

### Claim 12 (depends on 1)

The method of claim 1, wherein said oxide layer is formed such that it does not act as a mask in the step of patterning the first conductive pattern and the second conductive layer, thereby avoiding formation of a conductive stringer below said oxide layer when the first conductive pattern and the second conductive layer are patterned.

### Claim 13 (depends on 1)

The method of claim 1, wherein said oxide layer is formed to be confined within a boundary of the bottom portion of the first conductive pattern such that said oxide layer does not act as a mask in the step of patterning the first conductive pattern and the second conductive layer, thereby avoiding formation of a conductive stringer below said oxide layer when the first conductive pattern and the second conductive layer are patterned.

### Claim 14 (depends on 1)

The method of claim 1, wherein at least one of (i) an inclination of the sloping sidewall of the first conductive pattern and (ii) a thickness of said oxide layer is controlled so that the formed oxide layer is confined within a boundary of the bottom portion of the first conductive pattern, as a result of which said oxide layer does not act as a mask in the step of patterning the first conductive pattern and the second conductive layer, thereby avoiding formation of a conductive stringer below said oxide layer when the first conductive pattern and the second conductive layer are patterned.