# US 7,608,504 B2 · Memory and manufacturing method thereof

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- Number: US 7,608,504 B2
- Document ID: US7608504B2
- Status: Granted
- Kind: B2
- Application number: 11/468,311
- Filed: 2006-08-30
- Published: 2008-03-06
- Granted: 2009-10-27
- Earliest claimed: 2006-08-30
- Assignees: Macronix International Co., Ltd.
- Inventors: Chien-Hung Liu; Shou-Wei Huang; Ying-Tso Chen; Yu-Tsung Lin
- Web page: https://patentgrep.com/patent/US7608504B2

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10B 43/10: characterised by the top-view layout
- H10B 43/30: characterised by the memory core region
- H10D 89/10: Integrated device layouts
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

## Claims

### Claim 1

A method of manufacturing a memory, comprising:
providing a substrate;
forming a first oxide-nitride-oxide (ONO) structure on the substrate, comprising:
forming a bottom oxide layer on the substrate;
forming a nitride layer on the bottom oxide layer; and
forming a top oxide layer on the nitride layer;
forming a plurality of bit lines in the substrate, and all of the bit lines disposed in parallel, and step of forming the bit lines further comprising:
forming a patterned photo-resist layer on the first ONO structure, wherein the patterned photo-resist layer has a plurality of openings for exposing part of the first ONO structure; and
forming the bit lines in the part of the substrate corresponding to the openings; and
forming a plurality of word lines on the substrate, wherein the word lines are crossed with but not perpendicular to the bit lines.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the step of forming the bit lines in the part of the substrate corresponding to the openings further comprises:
forming the bit lines in the part of the substrate corresponding to the openings by using ion implantation process.

### Claim 3 (depends on 1)

The method according to claim 1, wherein between the step of forming the bit lines and the step of forming the word line further comprises:
removing part of the top oxide layer;
removing part of the nitride layer;
removing the patterned photo-resist layer;
forming a plurality of isolation layers on the bit lines; and
forming a plurality of second ONO structures on the substrate, wherein the second ONO structures are spaced by the isolation layers.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the step of forming the word lines further comprises:
forming the word lines on the substrate, wherein the word lines cover the second ONO structures and the isolation layers, and the word lines are crossed with the bit lines at 45 degrees.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the step of forming the word lines further comprises:
forming the word lines on part of the first ONO structure, wherein the word lines are crossed with the bit lines at 45 degrees.