# US 7,608,501 B2 · Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress

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- Number: US 7,608,501 B2
- Document ID: US7608501B2
- Status: Granted
- Kind: B2
- Application number: 11/425,942
- Filed: 2006-06-22
- Published: 2007-04-05
- Granted: 2009-10-27
- Earliest claimed: 2005-09-30
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Kai Frohberg; Carsten Peters; Matthias Schaller; Heike Salz
- Web page: https://patentgrep.com/patent/US7608501B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- Y10S 438/97: Specified etch stop material
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating strain by means of contact etch stop layers. Thus, a semiconductor device having different types of transistors may be provided, in which a high degree of metal silicide integrity as well as a highly efficient stress transfer mechanism is achieved.

## Claims

### Claim 1

A method, comprising:
selectively forming a first etch stop layer above only one of a first transistor element and a second transistor element;
forming a first contact etch stop layer above said first and second transistor elements and said first etch stop layer after selectively forming said first etch stop layer above only one of said first and second transistor elements, said first contact etch stop layer having a first specified intrinsic stress;
selectively removing a portion of said first contact etch stop layer formed above said one of said first transistor element and said second transistor element having formed thereabove said first etch stop layer by a selective etch process using said first etch stop layer as an etch stop; and
forming a second contact etch stop layer above said first and second transistor elements, said second contact etch stop layer having a second intrinsic stress that differs from said first intrinsic stress.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a second etch stop layer prior to forming said second contact etch stop layer and selectively removing a portion of said second contact etch stop layer above the other one of said one of said first transistor element and said second transistor element using said second etch stop layer as an etch stop.

### Claim 3 (depends on 1)

The method of claim 1, wherein selectively forming said first etch stop layer comprises depositing said first etch stop layer above said first and second transistor elements, forming a first mask layer covering said one of said first transistor element and said second transistor element and removing a non-masked portion of said first etch stop layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein said one of said first transistor element and said second transistor element receiving said first etch stop layer is an N-channel transistor element and said first contact etch stop layer comprises compressive stress.

### Claim 5 (depends on 1)

The method of claim 1, wherein said one of said first transistor element and said second transistor element receiving said first etch stop layer is a P-channel transistor element and said first contact etch stop layer comprises tensile stress.

### Claim 6

A method, comprising:
selectively forming a liner having a first type of intrinsic stress on a first transistor element while maintaining a second transistor element exposed;
selectively forming a first etch stop layer on said liner while maintaining said second transistor element exposed;
forming a first contact etch stop layer above said first and second transistor elements, said first contact etch stop layer having a second type of intrinsic stress other than said first type;
selectively removing a portion of said first contact etch stop layer formed above said first transistor element using said first etch stop layer as an etch stop;
removing said first etch stop layer; and
forming a second contact etch stop layer above said first and second transistor elements, said second contact etch stop layer having said first type of intrinsic stress.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming a second etch stop layer prior to forming said second contact etch stop layer and selectively removing a portion of said second contact etch stop layer above said second transistor element using said second etch stop layer as an etch stop.

### Claim 8 (depends on 6)

The method of claim 6, wherein selectively forming said liner and said first etch stop layer comprises depositing said liner with said first type of intrinsic stress, depositing said first etch stop layer on said liner, forming a mask layer covering said first transistor element and exposing said second transistor element and removing a non-masked portion of said liner and said first etch stop layer.

### Claim 9 (depends on 6)

The method of claim 6, wherein said first transistor element is a P-channel transistor and said second transistor element is an N-channel transistor.

### Claim 10 (depends on 9)

The method of claim 9, wherein said first type of intrinsic stress is a compressive stress.

### Claim 11 (depends on 6)

The method of claim 6, wherein said first transistor element is an N-channel transistor and said second transistor element is a P-channel transistor.

### Claim 12 (depends on 11)

The method of claim 11, wherein said first type of intrinsic stress is a tensile stress.

### Claim 13 (depends on 6)

The method of claim 6, wherein removing said first etch stop layer comprises exposing said liner and forming said second contact etch stop layer above said first and second transistor elements comprises forming said second contact etch stop layer above said exposed liner.