# US 7,608,499 B2 · Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same

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- Number: US 7,608,499 B2
- Document ID: US7608499B2
- Status: Granted
- Kind: B2
- Application number: 11/685,847
- Filed: 2007-03-14
- Published: 2008-01-31
- Granted: 2009-10-27
- Earliest claimed: 2006-07-31
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Karla Romero; Sven Beyer; Jan Hoentschel; Rolf Stephan
- Web page: https://patentgrep.com/patent/US7608499B2

## CPC

- H10P 30/204: {into Group IV semiconductors}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/208: {of electrically inactive species}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material layer is deposited over the first transistor element and the second transistor element. The stressed material layer is processed to form from the stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element. A pair of cavities is formed adjacent the gate electrode of the second transistor element. A pair of stress-creating elements is formed in the cavities and the hard mask is at least partially removed.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate comprising a first transistor element and a second transistor element, each of said first transistor element and said second transitor element comprising a gate electrode;
depositing a stressed material layer over said first transistor element and said second transistor element;
processing said stressed material layer to form from said stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element;
forming a pair of cavities in said substrate adjacent the gate electrode of the second transistor element;
forming a pair of stress-creating elements in said cavities; and
at least partially removing said hard mask.

### Claim 2 (depends on 1)

The method of claim 1, further comprising performing an ion implantation process adapted to amorphize portions of said semiconductor substrate adjacent the gate electrode of the first transistor element before the deposition of the stressed material layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein said ion implantation process comprises an implantation of ions of a dopant material.

### Claim 4 (depends on 2)

The method of claim 2, wherein said ion implantation process comprises an implantation of ions of at least one of a noble gas and a semiconductor material.

### Claim 5 (depends on 2)

The method of claim 2, further comprising amorphizing portions of the semiconductor substrate adjacent the gate electrode of the second transistor element before the deposition of the stressed material layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming an extended source region and an extended drain region adjacent at least one of the gate electrode of the first transistor element and the gate electrode of the second transistor element before the deposition of the stressed material layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising performing an annealing process after said formation of said stressed material layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein said annealing process comprises at least one of a rapid thermal annealing process and a furnace annealing process.

### Claim 9 (depends on 1)

The method of claim 1, wherein said hard mask and said sidewall spacers are substantially completely removed after said formation of said pair of stress-creating elements.

### Claim 10 (depends on 9)

The method of claim 9, wherein said removal of said hard mask and said sidewall spacers comprises performing an etching process.

### Claim 11 (depends on 1)

The method of claim 1, wherein said hard mask is partially removed after said formation of said pair of stress-creating elements, said partial removal of said hard mask comprising:
forming a mask over said second transistor element;
performing an anisotropic etching process adapted to remove portions of said hard mask over substantially horizontal portions of said first transistor element, wherein residues of said hard mask adjacent the gate electrode of the first transistor element are not removed and form second sidewall spacers; and
removing said mask.

### Claim 12 (depends on 1)

The method of claim 1, wherein said processing of said stressed material layer comprises:
forming a mask over said first transistor element, wherein said second transistor element is not covered by said mask;
performing an etching process adapted to remove portions of said stressed material layer over substantially horizontal portions of said second transistor element, wherein residues of said stressed material layer adjacent the gate electrode of the second transistor element are not removed and form said sidewall spacers, and wherein portions of the stressed material layer over the first transistor element are protected from being etched by said mask and form the hard mask; and
removing said mask.

### Claim 13 (depends on 1)

The method of claim 1, wherein said formation of said pair of cavities comprises performing an etching process adapted to remove a material of said semiconductor substrate, leaving said hard mask and said sidewall spacers substantially intact.

### Claim 14 (depends on 1)

The method of claim 1, wherein said formation of said pair of stress-creating elements comprises performing a selective epitaxial growth process adapted to deposit a stress-creating material adjacent the gate electrode of the second transistor element.

### Claim 15 (depends on 1)

The method of claim 1, wherein said stressed material layer comprises an intrinsic stress having an absolute value of about 900 Mpa or more.

### Claim 16 (depends on 1)

The method of claim 1, wherein said stressed material layer comprises an intrinsic tensile stress.

### Claim 17 (depends on 1)

The method of claim 1, wherein said first transistor element comprises an active region comprising a P-type dopant and said second transistor element comprises an active region comprising an N-type dopant.

### Claim 18

A method of forming a semiconductor structure, comprising:
forming a first gate electrode structure and a second gate electrode structure above a semiconductor substrate;
forming an extended source region and an extended drain region in said semiconductor substrate adjacent said second gate electrode structure;
depositing a stressed material layer over said first and second gate electrode structures;
forming sidewall spacers adjacent said second gate electrode structure, wherein forming said sidewall spacers comprises performing an etching process adapted to remove portions of said stressed material layer over said second gate electrode structure;
forming a first cavity in said extended source region adjacent said second gate electrode structure and a second cavity in said extended drain region adjacent said second gate electrode structure; and
forming a first stress-creating element in said first cavity and a second stress-creating element in said second cavity.

### Claim 19 (depends on 18)

The method of claim 18, wherein forming said first and second stress-creating elements comprises depositing a stress-creating material adjacent said second gate electrode structure by performing a selective epitaxial growth process.

### Claim 20 (depends on 19)

The method of claim 19, further comprising amorphizing portions of said semiconductor substrate adjacent said first and second gate electrode structures prior to depositing said stressed material layer, wherein amorphizing portions of said semiconductor substrate comprises performing an ion implantation process.

### Claim 21 (depends on 19)

The method of claim 19, wherein said first and second stress-creating elements comprise an intrinsic compressive stress.

### Claim 22 (depends on 21)

The method of claim 21, wherein said stress-creating material of said first and second stress-creating elements comprises silicon germanide.

### Claim 23 (depends on 19)

The method of claim 19, wherein said first and second stress-creating elements comprise an intrinsic tensile stress.

### Claim 24 (depends on 23)

The method of claim 23, wherein said stress-creating material of said first and second stress-creating elements comprises silicon carbide.