# US 7,608,498 B2 · Method of manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,498 B2 - Document ID: US7608498B2 - Status: Granted - Kind: B2 - Application number: 12/003,802 - Filed: 2008-01-02 - Published: 2008-07-31 - Granted: 2009-10-27 - Earliest claimed: 2005-10-24 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Takuya Kobayashi; Katsuyuki Sekine; Tomonori Aoyama; Hiroshi Tomita - Web page: https://patentgrep.com/patent/US7608498B2 ## CPC - H10P 14/693: {the material containing hafnium, e.g. HfSiOx or HfSiON} - C23C 16/401: {containing silicon} - H10D 84/0144: {Manufacturing their gate insulating layers} - H10D 84/0181: {Manufacturing their gate insulating layers} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)} - H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10P 14/6532: {by exposure to a plasma} - H10P 14/69392: {the material containing hafnium, e.g. HfO2} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal. ## Claims ### Claim 1 A method of manufacturing a semiconductor device comprising: forming a trench in an interlayer dielectric film on a semiconductor substrate, and forming a silicon dioxide film as a part of a gate dielectric film on the semiconductor substrate, the trench reaching the semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate dielectric film made of a HfSiO film as another part of the gate dielectric film, so that the HfSiO film is selectively deposited on the silicon dioxide film which is exposed at a bottom surface of the trench rather than on the silicon nitride film; and filling the trench with a gate electrode made of metal. ### Claim 2 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein: after depositing the silicon dioxide film as a part of the gate dielectric film, either one of or both nitriding and heat treating are performed to the HfSiO film. ### Claim 3 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, further including: setting a temperature condition of depositing the HfSiO film so that a deposition delay time attributable to a material of the silicon nitride film and a deposition delay time attributable to a material of the silicon dioxide film are mutually different. ### Claim 4 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein: the HfSiO film is deposited on the silicon dioxide film according to a MOCVD method. ### Claim 5 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein: the silicon dioxide film as a part of the gate dielectric film is formed by oxidizing the semiconductor substrate using thermal oxidation, radical oxidation, plasma oxidation, or chemical oxidation. ### Claim 6 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein: the HfSiO film is formed according to a chemical vapor deposition which uses at least tetrakis-dimethyl-amino-silicon and tetrakis-diethyl-amino-hafnium. ### Claim 7 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, the method further comprising: before forming the trench, forming a dummy gate in a region of the semiconductor substrate in which the gate electrode is formed; introducing impurity into the semiconductor substrate by using the dummy gate as a mask to form an extension layer; depositing a material of a sidewall protection film made of the silicon nitride film on the semiconductor substrate so as to cover the dummy gate; anisotropically etching the material of the sidewall protection film to form the sidewall protection film on the side surface of the dummy gate; depositing the material of the interlayer dielectric film on the semiconductor substrate so as to cover the dummy gate and the sidewall protection film; and flattening the interlayer dielectric film to expose the upper surface of the dummy gate, wherein: the trench is formed by removing the dummy gate. ### Claim 8 (depends on 1) The method of manufacturing a semiconductor device according to claim 1, wherein: a temperature of the depositing process of the gate dielectric film is within a range of 200 degrees centigrade to 260 degrees centigrade.