# US 7,608,497 B1 · Passivated tiered gate structure transistor and fabrication method

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- Number: US 7,608,497 B1
- Document ID: US7608497B1
- Status: Granted
- Kind: B1
- Application number: 11/517,685
- Filed: 2006-09-08
- Granted: 2009-10-27
- Earliest claimed: 2006-09-08
- Inventors: Ivan Milosavljevic; Adele Schmitz; Michael Antcliffe; Ming Hu; Lorna Hodgson
- Web page: https://patentgrep.com/patent/US7608497B1

## CPC

- H10D 64/411: {for FETs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

## Claims

### Claim 1

A method for fabricating a tiered gate structure transistor comprising:
forming a source and a drain;
forming a gate foot between the source and the drain, the gate foot comprising a conductive layer;
forming a passivation layer extending along an uppermost surface of the source and extending along an uppermost surface of the drain and on the gate foot such that a top portion of the gate foot is not covered with the passivation layer, the passivation layer directly contacting the uppermost surface of the source and the uppermost surface of the drain and surrounding sidewalls of the gate foot; and
forming a gate head on the gate foot and a portion of the passivation layer, wherein the passivation layer directly contacting the uppermost surface of the source and the uppermost surface of the drain and surrounding the sidewalls of the gate foot providing an additional support to the gate head and increasing a structural integrity of the tiered gate structure transistor.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the passivation layer comprises depositing a passivation layer on the gate foot and etching to remove a portion of the deposited passivation layer to uncover the top portion of the gate foot.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the passivation layer on the gate foot comprises depositing a layer of silicon nitride by using a plasma enhanced chemical vapor deposition process.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the gate head comprises forming the gate head generally centered over the gate foot.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the gate head comprises forming the gate head off-set over the gate foot.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the gate foot comprises forming the gate foot off-set between the source and the drain.

### Claim 7

A method for fabricating a tiered gate structure transistor comprising a source, a drain, and a gate, the method comprising:
forming a gate foot mask, the gate foot comprising a conductive layer on a substrate, the gate foot mask having an opening therethrough;
forming a gate foot in the opening of the gate foot mask;
removing the gate foot mask;
forming a passivation layer directly contacting an uppermost surface of the source, an uppermost surface of the drain, the substrate and the gate foot;
forming a gate head mask over the gate foot, the gate head mask having an opening therethrough exposing a portion of the passivation layer on a top portion of the gate foot;
removing the portion of the passivation layer to expose the top portion of the gate foot; and
forming a gate head on the gate foot;
removing the gate head mask while leaving an unremoved portion of the passivation layer directly contacting the uppermost surface of the source, the uppermost surface of the drain, the substrate and the gate foot.

### Claim 8 (depends on 7)

The method of claim 7, wherein forming the gate foot mask comprises depositing a low sensitivity resist over a high sensitivity resist.

### Claim 9 (depends on 7)

The method of claim 7, wherein forming the gate foot mask comprises:
forming a lower resist layer on the substrate;
forming an upper resist layer on the lower resist layer; and
forming an opening through the upper resist layer and the lower resist layer with the upper resist layer overhanging the lower resist layer in the opening.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the gate foot mask further comprises:
using an e-beam to expose the upper and lower resist layers of the gate foot mask; and
developing the upper and lower resist layers.

### Claim 11 (depends on 7)

The method of claim 7, wherein forming the gate head mask comprises:
forming a lower mask layer on the passivation layer;
forming an intermediate mask layer on the lower mask layer;
forming an upper mask layer on the intermediate mask layer; and
forming the opening through the upper mask layer, the intermediate mask layer, the lower mask layer to expose the portion of the passivation layer on the top portion of the gate foot.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the gate head mask further comprises:
using an e-beam to expose the upper mask layer, the intermediate mask layer, and the lower mask layer; and
developing the upper mask layer, the intermediate mask layer, and the lower mask layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein forming the gate head mask further comprises:
using a first e-beam to expose the upper mask layer and the intermediate mask layer;
developing the upper mask layer and the intermediate mask layer;
using a second e-beam to expose the lower mask layer; and
developing the lower mask layer.

### Claim 14 (depends on 11)

The method of claim 11, wherein forming the gate head mask comprises developing the intermediate mask layer and the lower mask layer with different developer types.

### Claim 15 (depends on 11)

The method of claim 11, wherein forming the gate head on the gate foot comprises depositing a gate head material into a dimple in the lower mask layer of the gate head mask.

### Claim 16 (depends on 7)

The method of claim 7, wherein forming the gate foot mask comprises forming the gate foot mask over a source and a drain on the substrate so that the gate foot is formed between the source and the drain.

### Claim 17 (depends on 7)

The method of claim 7, wherein forming the passivation layer on the substrate and the gate foot comprises depositing a layer of silicon nitride in a plasma enhanced chemical vapor deposition process.