# US 7,608,495 B1 · Transistor forming methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,495 B1 - Document ID: US7608495B1 - Status: Granted - Kind: B1 - Application number: 12/234,438 - Filed: 2008-09-19 - Granted: 2009-10-27 - Earliest claimed: 2008-09-19 - Assignees: Micron Technology, Inc. - Inventors: Jasper Gibbons - Web page: https://patentgrep.com/patent/US7608495B1 ## CPC - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and forming a gate line extending through the line openings, over opposing sidewalls, and over a top of the fin. Source/drain regions are in the fin. Another method includes forming an interlayer dielectric over areas of the fin intended for source/drain regions, forming contact openings through the interlayer dielectric, and forming a source/drain plug in contact with an exposed portion of the spacer and in electrical connection with the top, one of opposing endwalls, and both of the opposing sidewalls of the fin. ## Claims ### Claim 1 A transistor forming method comprising: forming an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate; removing some of semiconductor material of the island and forming a trench defining a fin of semiconductor material in the island, the fin having a top, opposing sidewalls, and opposing endwalls and a portion of the island remaining at a bottom of the trench; after forming the trench, forming a dielectric spacer in the trench over the bottom, the opposing sidewalls, and the opposing endwalls and laterally surrounding the fin, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness; forming line openings through the spacer and exposing through the line openings some of the semiconductor material of the island at the bottom of the trench and some of the semiconductor material of the opposing sidewalls of the fin; forming a gate line on and in contact with the semiconductor material exposed above the spacer and the semiconductor material exposed through the line openings, the gate line extending through the line openings, over the opposing sidewalls, and over the top of the fin; and in operational association with the gate line, forming source/drain regions in the fin. ### Claim 2 (depends on 1) The method of claim 1 wherein the island has a length greater than its width, the fin has a length greater than its width, the fin's length is less than the island's length, and the fin's width is than the island's width. ### Claim 3 (depends on 1) The method of claim 1 wherein the fin is laterally centered in the island. ### Claim 4 (depends on 1) The method of claim 1 wherein the trench laterally surrounds the fin and extends laterally from the fin at least to an outermost peripheral edge of the island. ### Claim 5 (depends on 1) The method of claim 1 wherein the forming of the trench comprises simultaneously etching the isolation material laterally surrounding the island and some of the semiconductor material of the island to a same elevational level as the bottom of the trench. ### Claim 6 (depends on 1) The method of claim 1 wherein the spacer extends laterally from the fin at least to an outermost peripheral edge of the island. ### Claim 7 (depends on 1) The method of claim 1 wherein the forming of the spacer comprises forming a dielectric spacer material over the opposing sidewalls and opposing endwalls and etching back some of the dielectric spacer material. ### Claim 8 (depends on 1) The method of claim 1 wherein the forming of the spacer comprises blanket depositing a dielectric spacer material over all of the island and etching back some of the dielectric spacer material. ### Claim 9 (depends on 1) The method of claim 1 wherein the forming of the gate line comprises: forming a gate dielectric material on and in contact with the semiconductor material exposed above the spacer and the semiconductor material exposed through the line openings; forming a gate stack material over the gate dielectric material; forming a gate cap material over the gate stack material; and forming a gate line from the gate dielectric material, gate stack material, and gate cap material. ### Claim 10 (depends on 1) The method of claim 1 further comprising forming gate line insulation on opposing sidewalls of the gate line before forming the source/drain regions. ### Claim 11 (depends on 1) The method of claim 1 wherein the forming of the transistor comprises forming an array of islands and transistors of like construction and the gate line is a word line further extending across the isolation material to another of the transistors. ### Claim 12 A transistor forming method comprising: forming an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate; removing some of semiconductor material of the island and forming a trench defining a fin of semiconductor material in the island, the fin have a top, opposing sidewalls, and opposing endwalls and a portion of the island remaining at a bottom of the trench; after forming the trench, forming a dielectric spacer in the trench over the bottom, the opposing sidewalls, and the opposing endwalls and laterally surrounding the fin, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness; forming a gate line on and in contact with the semiconductor material exposed above the spacer, the gate line extending over the opposing sidewalls and over the top of the fin; forming an interlayer dielectric over areas of the fin intended for source/drain regions; forming contact openings through the interlayer dielectric and exposing the areas intended for source/drain regions and at least a portion of the spacer proximate the areas; in operational association with the gate line, forming the source/drain regions in the fin; forming a source/drain plug in contact with the exposed portion of the spacer and in electrical connection with the top, one of the opposing endwalls, and both of the opposing sidewalls of the fin of one of the source/drain regions; and forming another source/drain plug in contact with the exposed portion of the spacer and in electrical connection with at least the top and both of the opposing sidewalls of the fin of another of the source/drain regions. ### Claim 13 (depends on 12) The method of claim 12 further comprising forming line openings through the spacer and exposing through the line openings some of the semiconductor material of the island at the bottom of the trench and some of the semiconductor material of the opposing sidewalls of the fin, wherein the gate line is also formed on and in contact with the semiconductor material exposed through the line openings, the gate line extending through the line openings, over the opposing sidewalls, and over the top of the fin. ### Claim 14 (depends on 12) The method of claim 12 wherein the spacer thickness constitutes a height offset between the source/drain plugs and the semiconductor material of the island at the bottom of the trench. ### Claim 15 (depends on 12) The method of claim 12 wherein the island has a length greater than its width, the fin has a length greater than its width, the fin's length is less than the island's length, the fin's width is than the island's width, and the fin is laterally centered in the island. ### Claim 16 (depends on 12) The method of claim 12 wherein the trench laterally surrounds the fin and extends laterally from the fin at least to an outermost peripheral edge of the island and the spacer extends laterally from the fin at least to the peripheral edge of the island. ### Claim 17 (depends on 12) The method of claim 12 wherein the forming of the trench comprises simultaneously etching the isolation material laterally surrounding the island and some of the semiconductor material of the island to a same elevational level as the bottom of the trench. ### Claim 18 (depends on 12) The method of claim 12 wherein the forming of the spacer comprises blanket depositing a dielectric spacer material over all of the island and etching back some of the dielectric spacer material. ### Claim 19 (depends on 12) The method of claim 12 wherein most of a height of the fin above the bottom of the trench is elevationally above the spacer thickness. ### Claim 20 (depends on 12) The method of claim 12 wherein forming the gate line comprises: forming a gate dielectric material on and in contact with the semiconductor material exposed above the spacer; forming a gate stack material on and in contact the gate dielectric material; forming a gate cap material on and in contact the gate stack material; and blocking with a mask and etching a gate line from the gate dielectric material, gate stack material, and gate cap material. ### Claim 21 (depends on 12) The method of claim 12 further comprising forming gate line insulation on opposing sidewalls of the gate line before forming the source/drain regions. ### Claim 22 (depends on 12) The method of claim 12 wherein the forming of the transistor comprises forming an array of islands and transistors of like construction, the spacer extends across the isolation material between the transistors, and the gate line is a word line further extending across the spacer to another of the transistors. ### Claim 23 (depends on 12) The method of claim 12 wherein the forming of the transistor comprises forming a double-gated transistor, the one of the source/drain regions comprising a drain region, the other of the source/drain regions comprising a source region shared between two gates, and the forming of the double-gated transistor comprising forming another drain plug in contact with an exposed portion of the spacer and in electrical connection with the top, another of the opposing endwalls, and both of the opposing sidewalls of the fin of another exposed drain region. ### Claim 24 A transistor forming method comprising: forming an island of semiconductor material laterally surrounded by electrical isolation material in a semiconductor substrate; removing some of semiconductor material of the island and forming a trench defining a fin of semiconductor material in the island, the fin have a top, opposing sidewalls, and opposing endwalls and a portion of the island remaining at a bottom of the trench; after forming the trench, forming a dielectric spacer in the trench over the bottom, the opposing sidewalls, and the opposing endwalls and laterally surrounding the fin, the spacer having a thickness and some of the semiconductor material of the fin being exposed elevationally above the spacer thickness; forming line openings through the spacer and exposing through the line openings some of the semiconductor material of the island at the bottom of the trench and some of the semiconductor material of the opposing sidewalls of the fin; forming a gate line on and in contact with the semiconductor material exposed above the spacer and the semiconductor material exposed through the line openings, the gate line extending through the line openings, over the opposing sidewalls, and over the top of the fin; forming gate line insulation on opposing sidewalls of the gate line; forming an interlayer dielectric over areas of the fin intended for source/drain regions; forming contact openings through the interlayer dielectric and exposing the areas intended for source/drain regions and at least a portion of the spacer proximate the areas; in operational association with the gate line, forming the source/drain regions in the fin through the contact openings; forming a source/drain plug in contact with the exposed portion of the spacer and in electrical connection with the top, one of the opposing endwalls, and both of the opposing sidewalls of the fin of an exposed source/drain region, the spacer thickness constituting a height offset between the source/drain plug and the semiconductor material of the island at the bottom of the trench; and forming another source/drain plug in contact with the exposed portion of the spacer and in electrical connection with at least the top and both of the opposing sidewalls of the fin of another exposed source/drain region, the spacer thickness constituting a height offset between the other source/drain plug and the semiconductor material of the island at the bottom of the trench. ### Claim 25 (depends on 24) The method of claim 24 wherein contact openings are self-aligned to the source/drain regions at least by the gate line insulation. ### Claim 26 (depends on 24) The method of claim 24 wherein the forming of the transistor comprises forming an array of islands and transistors of like construction and the gate line is a word line further extending across the isolation material to another of the transistors. ### Claim 27 (depends on 24) The method of claim 24 wherein the forming of the transistor comprises forming a double-gated transistor, the one of the source/drain regions comprising a drain region, the other of the source/drain regions comprising a source region shared between two gates, and the forming of the double-gated transistor comprising forming another drain plug in contact with an exposed portion of the spacer and in electrical connection with the top, another of the opposing endwalls, and both of the opposing sidewalls of the fin of another exposed drain region.