# US 7,608,489 B2 · High performance stress-enhance MOSFET and method of manufacture

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- Number: US 7,608,489 B2
- Document ID: US7608489B2
- Status: Granted
- Kind: B2
- Application number: 11/380,689
- Filed: 2006-04-28
- Published: 2007-11-01
- Granted: 2009-10-27
- Earliest claimed: 2006-04-28
- Assignees: International Business Machines Corporation
- Inventors: Dureseti Chidambarrao; Ricardo A. Donaton; William K. Henson; Kern Rim
- Web page: https://patentgrep.com/patent/US7608489B2

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- Y10S 438/938: Lattice strain control or utilization
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

## Claims

### Claim 1

A method of manufacturing a semiconductor structure:
forming, simultaneously, a layered structure with an underlying stress inducing material, in a p-type field-effect-transistor (PFET) channel region and a n-type field-effect-transistor (NFET) channel region;
protecting the NFET channel region while forming a layer over the underlying stress inducing material of the PFET channel region; and
etching an island in the NFET channel region and the PFET channel region, creating a higher resultant stress component in the NFET channel region; and
forming a stress inducing material in the etched portions of the PFET channel region creating an opposite stress component in the PFET channel region than in the NFET channel region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the layered structure with an underlying stress inducing material includes a top layer of Si and an underlying layer of SiGe, wherein the top layer of Si is of a different thickness respective to the NFET or PFET channel regions.

### Claim 3 (depends on 1)

The method of claim 1, wherein the PFET channel region is thicker than the NFET channel region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the PFET channel region has a top layer thicker than the NFET channel region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the layered structure with an underlying stress inducing material includes a top layer of Si and an underlying layer of SiGe, wherein the top layer of Si in the PFET channel region is thicker than the top layer of Si in the NFET channel region.

### Claim 6 (depends on 5)

The method of claim 5, wherein the germanium content of the SiGe is approximate from 20% and 30%.

### Claim 7 (depends on 5)

The method of claim 5, wherein a thickness of the top layer of Si in the PFET channel region is approximately 400 Å.

### Claim 8 (depends on 1)

The method of claim 1, wherein a thickness of an Si layer in the PFET channel region substantially reduces tensile stress in the PFET channel region prior to the forming of the stress inducing material in etched portions of the PFET channel region.

### Claim 9 (depends on 8)

The method of claim 8, wherein the stress inducing material in etched portions of the PFET channel region create compressive forces in the PFET channel region.

### Claim 10 (depends on 1)

The method of claim 1, wherein the etching and forming steps of the PFET channel region are provided while the NFET channel region is protected.