# US 7,608,488 B2 · Semiconductor memory device and method of manufacturing the same

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- Number: US 7,608,488 B2
- Document ID: US7608488B2
- Status: Granted
- Kind: B2
- Application number: 11/874,481
- Filed: 2007-10-18
- Published: 2008-10-23
- Granted: 2009-10-27
- Earliest claimed: 2006-10-27
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Yasuyuki Baba; Susumu Yoshikawa
- Web page: https://patentgrep.com/patent/US7608488B2

## CPC

- H10D 30/6894: {having one gate at least partly in a trench}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/48: with a tunnel dielectric layer also being used as part of the peripheral transistor
- H10B 41/49: comprising different types of peripheral transistor
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the height of first element-isolating insulating films of first memory cell array region of said first semiconductor device so as to be a predetermined height, by performing etching treatment under predetermined conditions using a first etching mask having a first opening for exposing the entirety of said first memory cell array region, and forming the height of second element-isolating insulating films of second memory cell array region and part of peripheral circuit region of said second semiconductor device so as to be the predetermined height, by performing etching treatment under said predetermined conditions using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region.

## Claims

### Claim 1

A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device wherein a cell array ratio at which an area occupied by a memory cell array region with respect to the entire surface area of a semiconductor substrate is a predetermined ratio and a second semiconductor device wherein said cell array ratio is smaller than said predetermined ratio, said manufacturing method comprising:
forming a height of first element-isolating insulating films in a first memory cell array region of said first semiconductor device, wherein first electrode layers and the first element-isolating insulating films are initially formed with a first height from said semiconductor substrate, so as to be a second height smaller than the first height, by performing etching treatment under predetermined conditions using a reactive ion etching method upon the entirety of the first memory cell array region using a first etching mask having a first opening for exposing the entirety of said first memory cell array region and a ratio at which the area of said first opening occupies part of the entire surface area of said semiconductor substrate is a predetermined opening ratio; and
forming a height of second element-isolating insulating films in a second memory cell array region and part of peripheral circuit region of said second semiconductor device, wherein second electrode layers and the second element-isolating insulating films are initially formed with the first height from said semiconductor substrate, so as to be the same as said second height, by performing etching treatment under conditions same as said predetermined conditions using a reactive ion etching method upon the second memory cell array region and the part of peripheral circuit region using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region wherein a ratio at which the sum of the areas of said second and third openings occupies part of the entire surface area of said second semiconductor substrate is the same as said predetermined opening ratio.

### Claim 2 (depends on 1)

The manufacturing method of a semiconductor memory device according to claim 1, wherein part of said peripheral circuit region is a dummy pattern region.

### Claim 3 (depends on 1)

The manufacturing method of a semiconductor memory device according to claim 1, wherein parts of said peripheral circuit region are a dummy pattern region and a region in which low breakdown voltage transistors are formed.

### Claim 4 (depends on 1)

The manufacturing method of a semiconductor memory device according to claim 1, wherein parts of said peripheral circuit region are a dummy pattern region and a region in which high breakdown voltage transistors are formed.

### Claim 5 (depends on 1)

The manufacturing method of a semiconductor memory device according to claim 1, wherein part of said peripheral circuit region is a region in which low breakdown voltage transistors are formed.

### Claim 6 (depends on 1)

The manufacturing method of a semiconductor memory device according to claim 1, wherein part of said peripheral circuit region is a region in which high breakdown voltage transistors are formed.

### Claim 7 (depends on 1)

The manufacturing method of a semiconductor memory device according to claim 1, wherein parts of said peripheral circuit region are regions in which low breakdown voltage transistors and high breakdown voltage transistors are formed.