# US 7,608,485 B2 · Highly reliable, cost effective and thermally enhanced AuSn die-attach technology

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- Number: US 7,608,485 B2
- Document ID: US7608485B2
- Status: Granted
- Kind: B2
- Application number: 11/530,276
- Filed: 2006-09-08
- Published: 2007-08-09
- Granted: 2009-10-27
- Earliest claimed: 2004-03-09
- Assignees: Infineon Technologies AG
- Inventors: Sam-Hyo Hong; Henrik Hoyer; Jeffrey Hume
- Web page: https://patentgrep.com/patent/US7608485B2

## CPC

- H10P 50/642: {Chemical etching}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10W 72/01331: {using blanket deposition}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a circuit, an integrated circuit package and methods for attaching integrated circuit dies or discrete power components to flanges of integrated circuit packages, each of the integrated circuit dies is sawed from a wafer. The thickness of the wafer is reduced by mechanical grinding, applying an isotropic wet chemical etching to the wafer to eliminate crystal defects, evaporating adhesion and diffusion barrier metals on the backside of the wafer, evaporating Au and Sn on the backside of the wafer, wherein the weight proportion of Au is equal to or larger than 85%, sawing the wafer into the circuit dies, and soldering each of the circuit dies to a respective flange of an integrated circuit package.

## Claims

### Claim 1

A method for attaching Si circuit dies to heat sinks, wherein each of said dies is sawed from a wafer, comprising the steps of:
reducing the thickness of said wafer by mechanical grinding;
applying an isotropic wet chemical etching to a backside of said wafer to eliminate crystal defects;
evaporating adhesion and diffusion barrier metals on the backside of said wafer;
evaporating Au and Sn on the backside of the wafer, wherein the weight proportion of Au in relation to the total amount of Au and Sn evaporated on the backside of the wafer is equal to or larger than 85%;
sawing the wafer into said circuit dies, and soldering each of said circuit dies to a respective heat sink; and
wherein the Au is deposited adjacent the evaporated adhesion and diffusion barrier metals and has a thickness such that at least a portion of the Au remains solid and does not diffuse when the dies are soldered to the respective heat sinks.

### Claim 2 (depends on 1)

A method according to claim 1, wherein said heat sink is a flange of an integrated circuit package.

### Claim 3 (depends on 1)

A method according to claim 1, wherein said heat sink is a heat sink on an RF power module or on a printed circuit board.

### Claim 4 (depends on 1)

A method according to claim 1, wherein said circuit die is an integrated circuit die, a power transistor or a capacitor, and wherein one or more of said circuit dies is soldered to a respective flange of said package.

### Claim 5 (depends on 1)

A method according to claim 1, wherein said isotropic wet chemical etching is an isotropic spin etching.

### Claim 6 (depends on 1)

A method according to claim 1, comprising the step of:
applying a roughening spin etching to the Si surface after the isotropic wet chemical etching to roughen the Si surface.

### Claim 7 (depends on 1)

A method according to claim 1, wherein said step of applying an isotropic wet chemical etching removes at least 25 μm of said wafer backside.

### Claim 8 (depends on 1)

A method according to claim 1, wherein said heat sink is pure Cu or an alloy of Cu and Zr or a Copper-Powder Copper Molybdenum-Copper (CPC) material or a Powder Copper Molybdenum (PCM) material.

### Claim 9 (depends on 1)

A method according to claim 1, wherein the step of evaporating Au and Sn on the backside of the wafer is performed by evaporating a first Au layer, an Sn layer and a second Au layer.

### Claim 10 (depends on 1)

A method according to claim 1, wherein the step of evaporating Au and Sn on the backside of the wafer is performed by evaporating a first Au layer and an Sn layer.

### Claim 11 (depends on 10)

A method according to claim 10, wherein said heat sink comprises a layer of plated Au which, together with the An and Sn layers on the wafer during the step of soldering forms an Au richer solder, than the eutectic composition of Au and Sn, with 80 weight % Au and 20 weight % Sn.

### Claim 12 (depends on 11)

A method according to claim 11, wherein said Au richer solder comprises between 86 and 89 weight percent Au.

### Claim 13 (depends on 2)

A method according to claim 2, wherein said step of evaporating adhesion and diffusion barrier metals comprises evaporating a Ti layer and evaporating a Pt layer on the backside of said wafer.

### Claim 14 (depends on 6)

A method according to claim 6, comprising the step of:
applying a round-up spin etch after the roughening etch to eliminate sharp re-entrant peaks.

### Claim 15

A method for manufacturing a Si circuit die to be attached to a heat sink, wherein said circuit die is sawed from a wafer, comprising the steps of:
reducing the thickness of said wafer by mechanical grinding;
applying an isotropic wet chemical etching to a backside of the wafer to eliminate crystal defects;
evaporating adhesion and diffusion barrier metals on the backside of said wafer;
evaporating Au and Sn on the backside of the wafer, wherein the weight proportion of Au, in relation to the total amount of Au and Sn evaporated on the backside of the wafer, is equal to or larger than 85%;
sawing the wafer into circuit dies; and
wherein the Au is deposited adjacent the evaporated adhesion and diffusion barrier metals and has a thickness such that at least a portion of the Au remains solid and does not diffuse when the dies are soldered to respective heat sinks.

### Claim 16 (depends on 15)

A method according to claim 15, wherein said heat sink is a flange of a circuit package.

### Claim 17 (depends on 15)

A method according to claim 15, wherein said heat sink is a heat sink on an Rf power module or on a printed circuit board.

### Claim 18 (depends on 15)

A method according to claim 15, wherein said circuit die is an integrated circuit die, a power transistor or a capacitor, and wherein one or more of said circuit dies is soldered to a respective flange of said package.

### Claim 19 (depends on 15)

A method according to claim 15, wherein said isotropic wet chemical etching is an isotropic spin etching.

### Claim 20 (depends on 15)

A method according to claim 15, comprising the step of:
applying a roughening etch to the Si after the isotropic wet chemical etching to roughen the Si surface.

### Claim 21 (depends on 15)

A method according to claim 15, wherein the step of evaporating Au and Sn on the backside of the wafer is performed by evaporating a first Au layer, a Sn layer and a second Au layer.

### Claim 22 (depends on 21)

A method according to claim 21, further comprising soldering the circuit die to said heat sink, wherein said first Au layer is so formed that at least a part of said first Au layer, being adjacent to a Pt layer, retains solid state during said step of soldering the circuit die to said heat sink.

### Claim 23 (depends on 15)

A method according to claim 15, further comprising soldering the circuit die to a flange of a circuit package, wherein said flange comprises a layer of plated Au which, together with the Au and Sn layers on the die during the step of soldering forms an Au richer solder.

### Claim 24 (depends on 23)

A method according to claim 23, wherein said Au richer solder comprises between 86 and 89 weight percent Au.

### Claim 25 (depends on 15)

A method according to claim 15, wherein said step of evaporating adhesion and diffusion barrier metals comprises evaporating a Ti layer and evaporating a Pt layer on the backside of said wafer.

### Claim 26 (depends on 20)

A method according to claim 20, comprising the step of:
applying a round-up etch after the roughening etch to eliminate sharp re-entrant peaks.