# US 7,608,484 B2 · Non-pull back pad package with an additional solder standoff

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- Number: US 7,608,484 B2
- Document ID: US7608484B2
- Status: Granted
- Kind: B2
- Application number: 11/554,728
- Filed: 2006-10-31
- Published: 2008-05-01
- Granted: 2009-10-27
- Earliest claimed: 2006-10-31
- Assignees: Texas Instruments Incorporated
- Inventors: Bernhard P. Lange; Anthony L. Coyle; Jeffrey Gail Holloway
- Web page: https://patentgrep.com/patent/US7608484B2

## CPC

- H10W 74/014: {using batch processing}
- H05K 3/341: Surface mounted components
- H10W 70/04: of leadframes
- H10W 70/457: {of metallic layers on leadframes}
- H10W 74/114: {by a substrate and the encapsulations}
- H05K 2201/10689: Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
- H05K 2201/10931: Exposed leads, i.e. encapsulation of component partly removed for exposing a part of lead, e.g. for soldering purposes
- H05K 2201/10969: Metallic case or integral heatsink of component electrically connected to a pad on PCB
- H05K 2201/10984: Component carrying a connection agent, e.g. solder, adhesive
- H10W 72/0198: {batch processes}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

## Claims

### Claim 1

A method of manufacturing a semiconductor package with a solder standoff comprising:
encapsulating a plurality of die on a lead frame strip, the lead frame strip comprising a plurality of package sites, and the package sites comprising a die pad and a plurality of lead pads;
forming a channel between the lead pads of nearby package sites without singulating the packages;
disposing solder on one of the lead pads, the die pad, or the lead pads and the die pad without substantially covering the channels with solder; and
singulating the packages.

### Claim 2 (depends on 1)

The method of claim 1 wherein the channel extends through the lead frame strip, but does not extend through the package.

### Claim 3 (depends on 1)

The method of claim 1 wherein the channel extends only partially through the lead frame strip.

### Claim 4 (depends on 1)

The method of claim 1 further comprising filling the channel with a resin.

### Claim 5 (depends on 4)

The method of claim 4 wherein the surface of the resin is substantially level with the surface of the lead frame strip.

### Claim 6 (depends on 4)

The method of claim 4 wherein the surface of the resin is not substantially level with the surface of the lead frame strip.

### Claim 7 (depends on 1)

The method of claim 1 wherein the solder is disposed on the lead pad by a planarization tool.

### Claim 8 (depends on 1)

The method of claim 1 further comprising planarizing the solder using a planarization tool.

### Claim 9 (depends on 8)

The method of claim 8 wherein a resin extending outward from the surface of the lead frame strip acts as a spacer for the planarization tool.

### Claim 10 (depends on 8)

The method of claim 8 wherein the planarization tool comprises a spacer for setting the solder standoff height.

### Claim 11 (depends on 10)

The method of claim 10 wherein the spacer is located at approximately the package corners.

### Claim 12 (depends on 1)

The method of claim 1 wherein the singulation of the packages utilizes a device of a lesser thickness than the device used to form the channel.

### Claim 13 (depends on 1)

The method of claim 1 wherein the singulation of the packages utilizes a cutting device of approximately the same thickness as the device used to form the channel.