# US 7,608,480 B2 · Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion

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- Number: US 7,608,480 B2
- Document ID: US7608480B2
- Status: Granted
- Kind: B2
- Application number: 11/880,162
- Filed: 2007-07-20
- Published: 2007-11-15
- Granted: 2009-10-27
- Earliest claimed: 2004-03-31
- Assignees: Casio Computer Co., Ltd.; CMK Corporation
- Inventors: Hiroyasu Jobetto
- Web page: https://patentgrep.com/patent/US7608480B2

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/01331: {using blanket deposition}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body and has a thickness substantially equal to the semiconductor constructing body. An one upper interconnecting layer is provided on the semiconductor constructing body and insulating layer, and electrically connected to the external connection electrodes. A vertical conducting portion extends through the insulating layer and electrically connects the metal foil and upper interconnecting layer.

## Claims

### Claim 1

A semiconductor device fabrication method comprising:
preparing a base member having at least one conductive surface formed at least at predetermined portions of a given surface of the base member, and separately arranging, on the at least one conductive surface at the predetermined portions of said given surface of the base member, a plurality of semiconductor constructing bodies each including a semiconductor substrate and a plurality of external connection bump electrodes formed on the semiconductor substrate;
forming an insulating layer on the base member around the semiconductor constructing bodies;
forming at least one upper interconnecting layer on one of the semiconductor constructing bodies and the insulating layer, such that the upper interconnecting layer is electrically connected to one of the external connection bump electrodes of the semiconductor constructing body;
forming a vertical conducting portion which electrically connects said given surface of the base member and the upper interconnecting layer through at least the insulating layer; and
cutting the insulating layer and base member between the semiconductor-constructing bodies, thereby obtaining a plurality of semiconductor devices each including at least one semiconductor constructing body.

### Claim 2 (depends on 1)

A method according to claim 1, wherein preparing the base member comprises preparing the base member having a base plate and a metal foil formed on at least said given surface of the base plate.

### Claim 3 (depends on 2)

A method according to claim 2, further comprising peeling the base plate from the metal foil after the insulating layer is formed on the base member around the semiconductor constructing bodies.

### Claim 4 (depends on 3)

A method according to claim 3, further comprising forming a plating layer on a lower surface of the metal foil after the base plate is peeled from the metal foil.

### Claim 5 (depends on 1)

A method according to claim 1, further comprising adhering the semiconductor substrates of the semiconductor constructing bodies onto the predetermined portions of the at least one conductive surface.

### Claim 6 (depends on 2)

A method according to claim 2, wherein each of the semiconductor constructing bodies includes a silicon oxide film formed on the semiconductor substrate, and an SOI integrated circuit formed on the silicon oxide film.

### Claim 7 (depends on 2)

A method according to claim 2, wherein each of the semiconductor constructing bodies includes an insulating film formed on the semiconductor substrate, interconnections formed on the insulating film, and a sealing film formed on the insulating film between the external connection bump electrodes.

### Claim 8 (depends on 1)

A method according to claim 1, wherein forming the vertical conducting portion comprises forming a through hole through the conductive surface and the base member.

### Claim 9 (depends on 1)

A method according to claim 1, wherein forming the vertical conducting portion includes forming a first through hole through a portion of the base member where the conductive surface is not formed, forming a second through hole through a portion of the base member where the conductive surface is formed, and electrically connecting the conductive surface and the upper interconnecting layer through the first and second through holes.

### Claim 10

A semiconductor device fabrication method comprising:
preparing a base member having a base plate and at least one metal foil, and separately arranging, on the base member, a plurality of semiconductor constructing bodies, each including a semiconductor substrate and a plurality of external connection electrodes formed on the semiconductor substrate;
forming an insulating layer on the base member around the semiconductor constructing bodies;
peeling the base plate from the metal foil, after the insulating layer is formed on the base member;
forming a plating layer on a lower surface of the metal foil, after the base plate is peeled from the metal foil;
forming at least one upper interconnecting layer on one of the semiconductor constructing bodies and the insulating layer, such that the upper interconnecting layer is electrically connected to one of the external connection electrodes of the semiconductor constructing body;
forming a vertical conducting portion which electrically connects one surface of the base member and the upper interconnecting layer through at least the insulating layer; and
cutting the insulating layer and base member between the semiconductor constructing bodies, thereby obtaining a plurality of semiconductor devices each including at least one semiconductor constructing body.

### Claim 11

A semiconductor device fabrication method comprising:
preparing a base member including a base plate and at least one metal foil formed at least at predetermined portions on the base plate, and separately arranging, on the at least one metal foil at the predetermined positions of the base plate, a plurality of semiconductor constructing bodies each including a semiconductor substrate and a plurality of external connection electrodes formed on the semiconductor substrate;
forming an insulating layer on the at least one metal foil of the base member around the semiconductor constructing bodies so as to be attached to the at least one metal foil;
removing the base plate from the metal foil while leaving the metal foil attached to the semiconductor constructing bodies and the insulating layer;
forming at least one upper interconnecting layer on one of the semiconductor constructing bodies and the insulating layer, such that the upper interconnecting layer is electrically connected to one of the external connection electrodes of the semiconductor constructing body;
forming a vertical conducting portion which electrically connects one surface of the base member and the upper interconnecting layer through at least the insulating layer; and
cutting the insulating layer and base member between the semiconductor constructing bodies, thereby obtaining a plurality of semiconductor devices each including at least one semiconductor constructing body.

### Claim 12

A semiconductor device fabrication method comprising:
preparing a base member having a base plate and a metal foil formed on at least one surface of the base plate, and separately arranging, on the base member, a plurality of semiconductor constructing bodies each including a semiconductor substrate and a plurality of external connection electrodes formed on the semiconductor substrate;
forming an insulating layer on the base member around the semiconductor constructing bodies;
peeling the base plate from the metal foil after the insulating layer is formed on the base member around the semiconductor constructing bodies;
forming at least one upper interconnecting layer on one of the semiconductor constructing bodies and the insulating layer, such that the upper interconnecting layer is electrically connected to one of the external connection bump electrodes of the semiconductor constructing body;
forming a vertical conducting portion which electrically connects said given surface of the base member and the upper interconnecting layer through at least the insulating layer; and
cutting the insulating layer and base member between the semiconductor-constructing bodies, thereby obtaining a plurality of semiconductor devices each including at least one semiconductor constructing body.