# US 7,608,479 B2 · Method of manufacturing semiconductor device and method of treating electrical connection section > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,608,479 B2 - Document ID: US7608479B2 - Status: Granted - Kind: B2 - Application number: 11/332,262 - Filed: 2006-01-17 - Published: 2006-07-20 - Granted: 2009-10-27 - Earliest claimed: 2005-01-19 - Assignees: Seiko Epson Corporation - Inventors: Hirohisa Nakayama; Shiro Sato; Masanobu Shoji; Hitoshi Nosaka - Web page: https://patentgrep.com/patent/US7608479B2 ## CPC - H05K 3/3489: Composition of fluxes; Application thereof; Other processes of activating the contact surfaces - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/652: Cross-sectional shapes - H10W 70/656: Fan-in layouts - H10W 70/66: Conductive materials thereof - H10W 70/68: Shapes or dispositions thereof - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/019: {of bond pads} - H10W 72/01971: {Cleaning, e.g. oxide removal} - H10W 72/07236: {Soldering or alloying} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/074: {of anisotropic conductive adhesives} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/251: {Materials} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, comprising: providing an electrical connection section and a protective film, the electrical connection section being electrically connected with a semiconductor substrate, a first part of the protective film covering at least a first area of a first surface of the electrical connection section, the first part of the protective film having a first face facing the first area of the first surface of the electrical connection section and a second face opposite to the first face, the protective film having an opening disposed on a second area of the first surface of the electrical connection section; applying a paste containing acid on the second area of the first surface of the electrical connection section and the second face of the first part of the protective film after providing of the electrical connection section and the protective film; removing the paste from the second area of the first surface of the electrical connection section by washing the electrical connection section; providing a solder to the electrical connection section through a flux after the removing of the paste; and providing the solder in such a manner that the solder is in touch with the second area of the first surface of the electrical connection section after the providing of the solder to the electrical connection section. ### Claim 2 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the paste applied in the applying of the paste includes a material that is the same as a material for the flux provided in the providing of the solder to the electrical connection section. ### Claim 3 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the paste applied in the applying of the paste includes a material containing an acid at a ratio higher than that of a material for the flux provided in the providing of the solder to the electrical connection section. ### Claim 4 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the paste applied in the applying of the paste includes a material containing an acid having a higher reducing power than that of an acid contained in the flux provided in the providing of the solder to the electrical connection section. ### Claim 5 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the applying of the paste and the removing of the paste are performed in air or in an oxygen atmosphere. ### Claim 6 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the acid contained in the paste is an organic acid. ### Claim 7 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the acid contained in the paste is an inorganic acid. ### Claim 8 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the semiconductor substrate is mounted on an interposer; and wherein the electrical connection section is a land formed on the interposer. ### Claim 9 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein the electrical connection section is an electrode pad formed on the semiconductor substrate. ### Claim 10 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein a resin layer is formed on the semiconductor substrate; and wherein the electrical connection section is a land formed on the resin layer. ### Claim 11 (depends on 1) The method of manufacturing a semiconductor device as defined in claim 1, wherein multiple electrical connection sections are arranged in rows and columns; and wherein the applying of the paste and the removing of the paste are carried out for the electrical connection sections positioned on an outer end of the rows and columns. ### Claim 12 (depends on 11) The method of manufacturing a semiconductor device as defined in claim 11, wherein the applying of the paste and the removing of the paste are carried out for the electrical connection sections positioned at outer corners of the rows and columns. ### Claim 13 (depends on 11) The method of manufacturing a semiconductor device as defined in claim 11, wherein the electrical connection sections are arranged in rows and columns in an area enclosing a specific area; and wherein the applying of the paste and the removing of the paste are carried out for the electrical connection sections positioned on an inner end of the rows and columns closest to the specific area.