# US 7,608,471 B2 · Method and apparatus for integrating III-V semiconductor devices into silicon processes

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- Number: US 7,608,471 B2
- Document ID: US7608471B2
- Status: Granted
- Kind: B2
- Application number: 11/199,663
- Filed: 2005-08-09
- Published: 2007-02-15
- Granted: 2009-10-27
- Earliest claimed: 2005-08-09
- Assignees: Avago Technologies General IP (Singapore) Pte. Ltd.
- Inventors: Sandeep R. Bahl
- Web page: https://patentgrep.com/patent/US7608471B2

## CPC

- H10P 90/1914: {using bonding}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10W 46/501: {for use before dicing}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Method and apparatus for fabricating semiconductor devices, for example, III-V semiconductor devices, having a desired substrate, for example, a silicon substrate. A method for fabricating semiconductor devices includes providing a semiconductor wafer that includes a plurality of semiconductor structures attached to a native substrate formed of a first substrate material, and a host substrate formed of a second substrate material. At least one subset of semiconductor structures of the plurality of semiconductor structures is transferred from the semiconductor wafer to the host substrate to provide a semiconductor device having a substrate formed of the second substrate material.

## Claims

### Claim 1

A system for fabricating silicon substrate semiconductor devices comprising III-V semiconductor structures, comprising:
a semiconductor wafer comprising a sapphire substrate, a separation layer, and an epitaxial layer disposed above the separation layer, a plurality of III-V semiconductor structures being formed in the epitaxial layer and arranged atop and attached too the separation layer, each of the plurality of III-V semiconductor structures being separated from the other III-V semiconductor structures by score lines etched therebetween and down to the underlying sapphire substrate through the separation layer disposed between the epitaxial layer and the sapphire substrate;
a host substrate comprising silicon;
a transfer mechanism configured to transfer, in succession, first and second subsets, respectively, of the plurality of III-V semiconductor structures from the semiconductor wafer to the host substrate, the transfer mechanism comprising means for positioning, in succession, the epitaxial layers and sapphire substrate corresponding to the first and second subsets of the semiconductor wafer such that the epitaxial layers face downwardly in respect of, and are positioned adjacent to, the silicon substrate, and means for aligning, in succession, each of the first and second subsets with corresponding metal bonding pads disposed at first and second locations on the silicon substrate, where the first location is different from the second location;
means for fusing, in succession, the epitaxial layers of the first and second subsets to the metal bonding pads disposed at the first and second locations on the silicon substrate, and
focused laser pulse means for selectively decomposing, in succession, the separation layers disposed between the first and second subsets and the sapphire substrate, and
means for removing from the silicon substrate those portions of the semiconductor wafer that are not fused to the silicon substrate.

### Claim 2 (depends on 1)

The system according to claim 1, wherein the transfer mechanism further comprises a pick and lace machine.

### Claim 3 (depends on 1)

The system according to claim 1, wherein the score lines define a plurality of substantially square or rectangular semiconductor structures.

### Claim 4 (depends on 1)

The system according to claim 1, wherein the epitaxial layer comprises at least one GaN-based compound.

### Claim 5 (depends on 4)

The system according to claim 4, wherein the at least one GaN-based compound is selected from the group consisting of GaN, AlGaN, AlN, InN, InGaN and InAlGaN.