# US 7,608,470 B2 · Interconnection device including one or more embedded vias and method of producing the same

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- Number: US 7,608,470 B2
- Document ID: US7608470B2
- Status: Granted
- Kind: B2
- Application number: 11/167,124
- Filed: 2005-06-28
- Published: 2006-12-28
- Granted: 2009-10-27
- Earliest claimed: 2005-06-28
- Assignees: Intel Corporation
- Inventors: Alexander Talalaevski; Eyal Bar-Sadeh; Shlomy Tubul
- Web page: https://patentgrep.com/patent/US7608470B2

## CPC

- B81C 1/00301: {Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/48: Insulating materials thereof
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/69: Insulating materials thereof
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- B81B 2207/096: through the substrate
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)

## Abstract

“An interconnection device comprises a Systems In Package (SIP) device, or Systems in Chip (SIC) device, including one or more embedded vias extending through a base substrate. A process to produce the interconnection device.”

## Claims

### Claim 1

A process comprising:
forming at least one inter-layer-dielectric section within a base substrate,
forming one or more embedded vias in said base substrate and in direct contact with said inter-layer dielectric section; and
attaching one or more electronic components to said base substrate before forming said vias.

### Claim 2 (depends on 1)

The process of claim 1, wherein attaching said one or more electronic components comprises attaching one or more elements of an embedded integrated circuit.

### Claim 3 (depends on 1)

The process of claim 1, wherein attaching said one or more electronic components comprises attaching one or more elements of a Micro-Electro-Mechanical Systems device.

### Claim 4 (depends on 1)

The process of claim 1, comprising applying a package over said one or more electronic components.