Method and apparatus for verifying system-on-chip model
AssigneeSamsung Electronics Co., Ltd.
InventorSoon-Wan Kwon
Life of this patent
Estimating the term…
Abstract
A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification method includes acquiring first request information and first response information; acquiring second request information and second response information; dividing the first and second request information and the first and second response information; comparing the divided first and second request information and comparing the divided first and second response information; and verifying a modeling result on the TL model depending on the comparison results.
Claims15
A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC), the method comprising:
- acquiring, by a Register Transfer Level (RTL) reader, from an RTL waveform indicating a simulation result on an RTL model, first request information of at least two sub-systems modeled as the RTL model during the SoC design, and first response information output from first slave models that have received the first request information;
- acquiring, by a TL waveform reader, from a TL waveform indicating a simulation result on the TL model, second request information of at least two sub-systems modeled as the TL model, and second response information output from second slave models that have received the second request information;
- dividing, by a sub-system divider, the first and second request information and the first and second response information separately for each of the sub-systems, using bus mastering information related to a right to access a slave model over a bus by the sub-systems, acquired from the TL waveform and the RTL waveform;
- comparing, by an equivalence and data inconsistency comparator, the divided first and second request information with each other and comparing the divided first and second response information separately for the sub-systems of the RTL model and the sub-systems of the TL model;
- and
- verifying, by the equivalence and data inconsistency comparator, a modeling result on the TL model depending on the comparison results.
An apparatus for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC), the apparatus comprising:
- a Register Transfer Level (RTL) waveform reader for reading an RTL waveform indicating a simulation result on an RTL model, and outputting first request information of at least two sub-systems modeled as the RTL model during SoC design, and first response information output from first slave models that have received the first request information;
- a TL waveform reader for reading and outputting, from a TL waveform indicating a simulation result on the TL model, second request information of at least two sub-systems modeled as the TL model, and second response information output from second slave models that have received second request information;
- a sub-system divider for dividing the first and second request information and the first and second response information output from the RTL waveform reader and the TL waveform reader separately for each of the sub-system, using bus mastering information related to a right to access a slave model over a bus by the sub-systems;
- and
- an equivalence and data inconsistency comparator for comparing the divided first and second request information and the divided first and second response information separately for each of the sub-systems, and comparing the divided first and second request information with each other separately for sub-systems of the RTL model and sub-system of the TL model, and comparing the divided first and second response information with each other separately for the sub-systems of the RTL model and the sub-system of the TL model, thereby verifying a modeling result on the TL model.
Dependencies are inferred from the claim text.