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US 7,607,115 B1Granted
System, method and computer program product for timing-independent sequential equivalence verification
AssigneeCalypto Design Systems, Inc.
InventorsVenkatram Krishnaswamy, Shusaku Yamamoto, Junichi Tatsuda
Life of this patent
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Abstract
A system, method and computer program product are provided for verifying sequential equivalence. In use, input is fed to a first system and a second system in a timing-independent manner to generate output. To this end, sequential equivalence of the first system and the second system may be verified, based on the output.
Claims17
A verification method, comprising:
- feeding a first system and a second system in a timing-independent manner to generate output from the first system and the second system;
- and
- verifying a sequential equivalence of the first system and the second system, based on the output from the first system and the second system utilizing a processor;
- wherein a logical equivalence of the first system and the second system is verified, and the output from the first system and the second system has sequential differences and timing differences.
1 more element
A computer program product embodied on a tangible computer readable medium, comprising:
- computer code for feeding a first system and a second system to generate output from the first system and the second system;
- and
- computer code for verifying a sequential equivalence of the first system and the second system, based on the output from the first system and the second system;
- wherein the verification is performed in a timing-independent manner;
- wherein a logical equivalence of the first system and the second system is verified, and the output from the first system and the second system has sequential differences and timing differences.
2 more elements
A system including a tangible computer readable medium, comprising:
- a first design;
- a second design;
- and
- a verification wrapper, the verification wrapper capable of feeding the first design and the second design in a timing-independent manner to generate output from the first design and the second design, and verifying a sequential equivalence of the first design and the second design, based on the output from the first design and the second design;
- wherein a logical equivalence of the first design and the second design is verified, and the output from the first design and the second design has sequential differences and timing differences.
2 more elements
Dependencies are inferred from the claim text.