Method and apparatus for encoding and decoding data
AssigneeMotorola, Inc.
InventorsYufei Wu Blankenship, T. Keith Blankenship, Ajit Nimbalker
Life of this patent
Estimating the term…
Abstract
A method and apparatus for encoding and decoding data is provided herein. During operation, A structured parity-check matrix H is provided to the encoder and decoder, where H is an m by n matrix and an expansion of a model matrix Hbm of size mb by nb, where m=mb×z and n=nb×z. For a given code rate, multiple code sizes are accommodated by allowing both the model matrix size nb and the expansion factor z to vary.
Claims20
A method for operating a transmitter that generates parity-check bits p=(p0, . . . , pm-1) based on an information block s=(s0, . . . , sk-1), the method comprising the steps of:
- receiving the information block s=(s0, . . . , sk-1);
- using a matrix H to determine the parity-check bits;
- and
- transmitting the parity-check bits along with the information block;
- wherein H is an m by n matrix and an expansion of a model matrix Hbm of size mb by nb and wherein m=mb×z and n=nb×z, and wherein model matrix size nb varies and expansion factor z varies for a given code rate, 1≦z≦z0, to provide H matrices of different sizes.
A method for estimating an information block s=(s0, . . . , sk-1), the method comprising the steps of:
- receiving a signal vector y=(y0, . . . , yn-1);
- and
- using a matrix H to estimate the information block (s0, . . . , sk-1);
- wherein H is an m by n matrix and an expansion of a model matrix Hbm of size mb by nb and wherein m=mb×z and n=nb×z, and wherein model matrix size nb varies and expansion factor z varies for a given code rate, 1≦z≦z0, to provide H matrices of different sizes.
An apparatus comprising:
- logic circuitry receiving an information block s=(s0, . . . , sk-1) and using a matrix H to determine parity-check bits, wherein H is an m by n matrix and an expansion of a model matrix Hbm of size mb by nb and wherein m=mb×z and n=nb×z, and wherein model matrix size nb varies and expansion factor z varies for a given code rate, 1≦z≦z0, to provide H matrices of different sizes;
- and
- a transmitter transmitting the parity-check bits along with the information block.
An apparatus comprising:
- a receiver receiving a signal vector y=(y0, . . . , yn-1);
- and
- logic circuitry using a matrix H to estimate an information block (s0, . . . , sk-1), wherein H is an m by n matrix and an expansion of a model matrix Hbm of size mb by nb and wherein m=mb×z and n=nb×z, and wherein model matrix size nb varies and expansion factor z varies for a given code rate, 1≦z≦z0, to provide H matrices of different sizes.
Dependencies are inferred from the claim text.