Loading patent…
AssigneeAgere Systems Inc.
InventorsMark Andrew Bickerstaff, Graeme Edwin Pope, Benjamin John Widdup, Graeme Kenneth Woodward
Estimating the term…
Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.
A decoder for an LDPC code based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of said plurality of sub-matrices has a single non-zero entry, comprising:
A decoder for an LDPC code based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of said plurality of sub-matrices has a single non-zero entry, comprising:
A decoder for an LDPC code based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of said plurality of sub-matrices has a single non-zero entry, comprising:
A method for decoding an LDPC code based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of said plurality of sub-matrices has a single non-zero entry, each of said sub-matrices having at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, said method comprising:
A method for decoding an LDPC code based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of said plurality of sub-matrices has a single non-zero entry, each of said sub-matrices having at least one associated Phi-node, said method comprising:
Dependencies are inferred from the claim text.