System and method for performing high speed memory diagnostics via built-in-self-test

An integrated circuit, comprising:

• a memory;
• first means for executing a test algorithm that provides test information to said memory in response to a clock signal over a plurality of clock cycles, said test information comprising expected test data, and said test algorithm having a starting point;
• second means for during execution of said test algorithm from said starting pint, cyclically receiving actual test values from said memory in response to said clock signal and comparing said expected test data to said actual test values a manner that generates a fail signal each time any one of said actual test values does not match said expected test data;
• a data register for holding each of said actual test values in seriatim;
• and
• third means for causing said first means to reload said data register with the one of said actual test values corresponding to a desired occurrence of said fail signal by re-executing said test algorithm from said starting point and stopping the re-execution of said test algorithm on the re-occurrence of the desired occurrence of said fail signal such that the one of said actual test values corresponding to the desired occurrence of said fail signal is contained in said data register when the re-execution of said algorithm is stopped.

A method of testing an integrated circuit memory of an integrated circuit using built-in self-test circuitry and fail logic circuitry having a fail-signal latency of at least one clock cycle, comprising:

• implementing via the built-in self-test circuitry a first pass of a memory testing algorithm to determine a fail in the integrated circuit memory as a function of faulty actual data being contained in a test data register;
• generating a fail signal based on said faulty actual data being contained in said test data register;
• and
• causing said built-in self test circuitry to perform a second pass of said memory testing algorithm as a function of each of said fail signal and the fail-signal latency to reload said faulty actual data into said test data register.