US 7,607,059 B2 · Systems and methods for improved scan testing fault coverage

Abstract

Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embodiment, an LBIST system comprises a plurality of scan latches and forcing logic coupled to a first set of the scan latches which provide inputs to selected target logic. The forcing logic is configured to overwrite values stored in the first set of scan latches with desired values. In one embodiment, the forcing logic includes a bypass path that enables shifting of unaltered bit patterns around the first set of scan latches. Bits in the bypass path may be inverted when the bypass path is not being used in order to help detect errors in the operation of the bypass path.

Claims22

Dependent claims

An integrated circuit test system comprising:

a plurality of scan latches configured as a single scan chain, wherein each of the plurality of scan latches is coupled to a corresponding input of target logic, wherein the plurality of scan latches are configured to receive and store bit patterns;
and
forcing logic coupled to a first set of the plurality of scan latches and configured to selectively force values stored in the first set of scan latches to desired values, wherein the desired values replace the values in the first set of scan latches, wherein the forcing logic comprises one or more logic gates coupled to the inputs of each of the first set of scan latches, wherein each logic gate is configured to receive as inputs a forcing signal and an output of a preceding one of the plurality of scan latches and to provide an output of the logic gate to a following one of the plurality of scan latches, wherein when the forcing signal is asserted, each of the first set of scan latches is loaded with a predetermined forced value.

Dependencies are inferred from the claim text.

Systems and methods for improved scan testing fault coverage

Life of this patent

Systems and methods for improved scan testing fault coverage

Life of this patent

Abstract

Claims22