Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip

A system on a chip (SOC) comprising:

• a plurality of logic cores and processing elements;
• and
• an apparatus embedded in the SOC, the apparatus interfacing to the plurality of logic cores and processing elements in the SOC, the apparatus comprising:
• a hard macro, wherein an interface of the hard macro comprises SOC input and output (I/O) pins, a scan in pin, a scan out pin, and a test pin;
• a test wrapper surrounding the hard macro interface, the test wrapper shifting a known test data pattern for input to the hard macro interface during a test mode, wherein the test wrapper comprises input and output pins that interface to the hard macro interface, and a plurality of flip flops and multiplexers only;
• and
• a scan chain in the test wrapper, the scan chain comprising a series of flip-flops that shifts the known test data pattern through the multiplexers in the test wrapper that output data through, the hard macro interface into the hard macro in a test mode of the SOC.