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US 7,607,055 B2Granted
Semiconductor memory device and method of testing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDae-Hee Jung, Chul-Woo Park, Seung-Young Seo
Life of this patent
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Abstract
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.
Claims17
A semiconductor memory device comprising:
- a plurality of pads;
- at least one first built in self test (BIST) circuit configured to generate first test pattern data;
- and
- at least one second BIST circuit configured to receive the first test pattern data as received first test pattern data and compare the received first test pattern data to second test pattern data;
- wherein:
- each first BIST circuit and each second BIST circuit is coupled to a pad different from a pad coupled to another first BIST circuit or second BIST circuit;
- each first BIST circuit is configured to output the first test pattern data through the pad corresponding to that first BIST circuit;
- and
- each second BIST circuit is configured to receive the first test pattern data through the pad corresponding to that second BIST circuit;
- and
- wherein:
- each second BIST circuit is further configured to generate third test pattern data and output the third test pattern data;
- and
- each first BIST circuit is further configured to receive the third test pattern data as received third test pattern data and compare the received third test pattern data to fourth test pattern data.
11 more elements
A method of testing a semiconductor memory device;
- comprising:
- generating a first test pattern data in the semiconductor memory device;
- outputting the first test pattern data through a first pad of the semiconductor memory device;
- receiving the first test pattern data through a second pad of the semiconductor memory device;
- generating a second test pattern data substantially equivalent to the first test pattern data output through the first pad of the semiconductor memory device;
- comparing the second test pattern data with the first test pattern data received through the second pad of the semiconductor memory device;
- and
- switching an output of a data buffer from a pipeline data path to a comparator
- wherein receiving the first test pattern data further comprises receiving the first test pattern data through the data buffer.
6 more elements
A buffer circuit and built in self test (BIST) circuit for a semiconductor memory device comprising:
- a BIST controller configured to generate an enable signal, a test mode signal, and a test pattern generation control signal;
- an output buffer responsive to the enable signal;
- an input buffer responsive to the enable signal;
- a pattern generator configured to generate a test pattern in response to the a test pattern generation control signal;
- a mode selector configured to select between data from a memory core and the test pattern in response to the test mode signal, and provide the selected data or test pattern to the output buffer;
- a comparator;
- a switch configured to switch a received test pattern from the input buffer selectively between the memory core and the comparator;
- an ordering circuit configured to generate a flag in response to the comparison of the test pattern and the received test pattern;
- and
- a pipeline data path coupled between the output buffer and the memory core;
- wherein the mode selector is coupled between the memory core and the pipeline data path and further configured to provide the selected data or test pattern to the output buffer through the pipeline data path;
- and
- wherein the comparator is configured to compare the test pattern with a received test pattern.
10 more elements
Dependencies are inferred from the claim text.