US 7,607,029 B2 · PCI express link state management system and method thereof

Abstract

A PCI Express link state management system and method thereof is disclosed. The PCI Express link power state management system includes an upstream device, a downstream device and a link. First, the upstream device outputs a configuration request to the downstream device so as to change a device power state of the downstream device. At the time, the link is in a first link state. Next, the downstream device outputs a power entering signal to the upstream device. Following that, the upstream device outputs a power request acknowledging signal to the downstream device in response to the power entering signal and a time period is counting. Finally, the downstream device re-outputs the power entering signal if the link does not enter to an electrical idle state when the time period is expired.

Claims20

Dependent claims

A method for managing link state, applied to a link connected between a upstream device and a downstream device, the method comprising:

outputting a configuration request to the downstream device to change a device power state of the downstream device, wherein the link is in a first link state;
outputting a power entering signal to the upstream device;
outputting a power request acknowledging signal to the downstream device in response to the power entering signal and counting a time period;
and
re-outputting the power entering signal if the link does not enter to an electrical idle state when the time period is expired.

2 more elements

Dependencies are inferred from the claim text.

PCI express link state management system and method thereof

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PCI express link state management system and method thereof

Life of this patent

Abstract

Claims20