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US 7,606,998 B2Granted
Store instruction ordering for multi-core processor
AssigneeCavium Networks, Inc.
InventorsDavid H. Asher, Richard E. Kessler, Yen Lee
Life of this patent
Estimating the term…
Abstract
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.
Claims19
A processor comprising:
- a write buffer having a plurality of write buffer entries for storing data to be stored in external memory;
- and
- a system interface, the system interface comprising:
- a first logic circuit that sends data from write buffer entries to external memory;
- and
- a second logic circuit which upon detecting execution of a store ordering instruction ensures that earlier stores complete before subsequent stores complete, the first and second logic circuits further configured to prevent overflow of an ordering queue and to eliminate stalling of any store ordering instructions at the system interface.
3 more elements
A method for ordering store data in a processor comprising:
- storing data to be stored in external memory in a write buffer entry in a write buffer;
- sending data stored in the write buffer to the external memory;
- and
- upon detecting execution of a store ordering instruction, ensuring that earlier stores complete before subsequent stores complete, preventing overflow of an ordering queue and eliminating stalling of any store ordering instructions at a system interface of the processor.
1 more element
A network services processor comprising:
- cache memory;
- and
- at least one processor core, the processor core comprising:
- a write buffer having a plurality of write buffer entries for storing data to be stored in the cache memory;
- and
- a system interface, the system interface comprising:
- a first logic circuit sending data from write buffer entries to the cache memory;
- and
- a second logic circuit which upon detecting execution of a store ordering instruction ensures that earlier stores complete before subsequent stores complete, the first and second logic circuits further configured to prevent overflow of an ordering queue and eliminating stalling of any store ordering instructions at the system interface.
6 more elements
Dependencies are inferred from the claim text.